- Chapter 1 Introduction to Computer Systems
- 1.2 Computer Hardware
A program that can be executed in a computer is composed of instructions, so the process of executing a program by a computer is the process of executing a set of instructions in a given order.
An instruction is divided into two parts: (1) opcode (2) address code
The basic components that make up a computer are: central processing unit (CPU, arithmetic unit and controller), memory and input and output devices.
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- 1.3 Computer software
There are two kinds of translation programs: compiler and interpreter.
The compiler is to translate all the statements in the source program written by people into a machine language program, and then execute the machine language program.
The interpreter executes a statement of the source program immediately after translating it into machine language, and then translates and executes the next statement.
- Chapter 4 Main Memory
4.1 Main memory classification, technical indicators and basic operations
Type of main memory: (1) Random access memory RAM: readable, writable, volatile, data disappears after power failure
- Non-volatile memory: data will not be lost after power loss
Specifications: Main memory capacity, memory access time and storage cycle
Basic operation:
- Read: The CPU sends the address of the information word to AR, and sends it to the main memory via the address bus; the CPU sends a "read" request to the control line; the main memory responds through the ready line, if the ready signal is 1, it indicates the content of the memory has been taken out and placed on the data bus, sent to DR
- Take: the same
Asynchronous work between CPU and main memory
4.3 Non-volatile semiconductor memory
(1) Read-only memory ROM: The content is written when it is remanufactured by the manufacturer, and it can only be read and cannot be written in the future.
(2) Programmable read-only memory PROM: write-once memory
(3) Erasable Programmable Read-Only Memory (EPROM): UV erasable, unlimited programming times
(4) Electrically Erasable Programmable Read-Only Memory (E2PROM): Electrically erased, the number of times of repeated rewriting is limited
(5) Fast erasing read-write memory Flash Memory: erased by electricity, is the only memory with large storage capacity, non-volatile, low price, online rewriting and high-speed reading, also known as flash memory
4.4 Composition and Control of Memory
- memory capacity expansion
- bit extension
Bit expansion refers to the expansion of the word length with multiple memory chips. The connection method is to lead out the addresses, chip selections, read and write control terminals and data terminals of the multi-chip memories respectively. Two 16K*4-bit chips are used to form a 16K*8-bit memory, the memory word length is 8 bits, each chip word length is 4 bits, and each chip has 14 address line leads and 4 data line leads.
- word expansion
Word expansion refers to increasing the number of words in memory. When the static memory performs word expansion, the address lines, data lines and read/write control lines of each chip are connected in parallel, and the address range of each chip is distinguished by the chip select signal.
- word extension
- storage control
The refresh logic is prepared for the dynamic MOS random access memory, and the information of the memory is not lost through regular refresh. Dynamic memory is refreshed by "reading". The time interval between the start of the last refresh of the entire memory and the start of the refresh of the entire memory this time is called a regeneration cycle or a refresh cycle, and is generally 2ms.
Assuming that the memory has 1024 rows, the method of refreshing the 1024 rows in a scattered manner within 2ms is called distributed refresh. The specific method is to divide the refresh cycle by the number of rows to obtain the maximum time interval t between two refresh operations, and use a logic circuit to generate a refresh request every time t.
4.5 Multi-Bank Interleaved Memory
The large-capacity main memory in the computer consists of multiple storage banks, each of which has its own read and write routes, address registers and data registers, which are called storage modules. This multi-module memory can achieve overlapping and interleaving. If the addressing is cross-addressed on M modules (M=2^m), it is called modulo-M cross-addressing.
It is assumed that the memory includes M modules, the capacity of each module is L, each storage module performs low-order cross-addressing, and consecutive addresses are distributed in adjacent modules. The address number of the ith module Mi should be given as follows:
M*j+i, where j=0, 1, 2,..., L-1 i=0, 1, 2..., M-1
This addressing method uses the low-order field of the address code to select different memory modules after decoding, and the high-order field points to the storage word inside the corresponding module. This addressing method will greatly improve the effective access speed of the main memory.
CPU and IOP access to memory is achieved through the main memory control unit.
When the CPU issues a read or write request operation, the memory bank is selected by the cross addressing bit, and the busy trigger in the memory bank control unit is queried whether it is 1. When the trigger is 1, it means that the memory bank is performing a read or write operation. It is necessary to wait for the end of the operation to set the busy trigger to 0 before responding to a new read or write request. When the memory bank completes the read and write operations , send a reply signal to the CPU, if the CPU continues to read and write operations, it will send the next address code and its read and write commands to the storage control unit.
- Chapter 5 Command System
5.2 Instruction format
An instruction generally contains the following information: (1) the opcode (2) the address of the operand (3) the storage address of the operation result (4) the address of the next instruction. An instruction includes two kinds of information, namely the opcode and the address code.
According to the frequency of the instructions in the program, opcodes of different lengths are assigned, which is called Huffman coding
5.3 addressing mode
- base addressing
Set a dedicated base register in the computer, or specify a general register as the base register by the instruction. The address of the operand is obtained by adding the contents of the base register and the address code A of the instruction. In this case, the address code A is usually called the displacement amount.
- Indexed addressing
The address A given by the address code part of the instruction and the contents of the specified index register X are added by the adder, and the resulting sum is used as the address to read the required operand from the memory. When there is a base register in the computer, the content of the base register is added when calculating the effective address.
Note: The difference between base addressing and index addressing: the address is the offset in base addressing, the first address in index addressing, and the content stored by the register in base addressing is the base address, In indexed addressing is an offset.
- Chapter 6 Central Processing Units
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- The function of the controller
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Fetching instructions, analyzing instructions, executing instructions, controlling program and data input and result output, handling exceptions and certain requests (interrupt requests, DMA request signals)
6.1.3 Instruction execution process
Take addition as an example
- Fetch the instruction from memory, send it to the instruction register, and decode the opcode
control signal:
PC->AB: command address to send address bus
W/R=0: perform read operation
M/IO=1: memory
DB->IR: get value to instruction register
PC+1: Program Counter+1
The memory reads the instruction address on the address bus, and fetches the instruction of the corresponding address to the DB
- Calculate the data address in the ALU, and send the calculated effective address to the address register AR
control signal:
① Take two source operands (for address calculation)
rs1->GR: register address to send general register
(rs1)->ALU: The contents of the register are sent to the ALU
disp->ALU: The offset is sent to ALU
②Addition operation
“+”:
③The effective address is sent to the address register: ALU->AR
- Fetch to memory
①Data address sending address bus: AR->AB
②Send memory access control commands
M / I = 1
W/R=0
③Data send data register: DB->DR.
- Perform the addition operation, send the result to the register, and set the status bits N, Z, V, C according to the operation result
①Two source operands are sent to ALU
rs->GR: another register is sent to the general register GR
rs->ALU:GR is sent to ALU
DR->ALU: The data in the data register is sent to the ALU
②Addition operation+
③Send the result: ALU->GR
6.2.1 The basic concept of microprogram control
Micro-operation: The function of an instruction is to perform a series of basic operations in one order, these operations are called micro-operations
Microinstruction: A group of micro-operations.
Microcommands: micro-operations that make up a microinstruction
Microprogram: One instruction is one microprogram. A collection of microinstruction sequences is called a microprogram.
Control memory: Microprograms are generally stored in a dedicated memory. Since the memory is mainly stored for the control command (signal) and the address of the next executed microinstruction, it is called the control memory.
6.2.2 The basic principle of realizing microprogram control
After the instruction is fetched into the IR, it is decoded according to the opcode to obtain the address of the first microinstruction of the corresponding instruction.
The instruction decoding unit can be composed of read-only memory, and this opcode is used as the input address of the read-only memory. The content of this unit is the address of the corresponding microinstruction in the control storage, and the microinstruction is fetched from the control memory according to this address, and Store it in the microinstruction register.
CLK2 is divided by two to obtain CLK, and then CLK is divided to obtain T1, and T2 is obtained by inverting the phase of T1.
Machine Cycles: The time of the micro-operation with the longest execution time
- Chapter 7 Storage Systems
7.3.1 Main memory-auxiliary memory level information transfer unit and storage management
Segment management: Segments are divided into multiple independent parts according to the logical structure of the program by utilizing the modular nature of the program. Use the segment table to indicate the location of each segment in main memory. Each segment has its name, segment start address, segment length, etc.
Advantages: The division of the segment corresponds to the division of the program; logical independence, easy to compile, manage, modify, protect, share
Disadvantages: It is easy to leave a lot of spare fragmentary storage controls between segments, which is not easy to use, resulting in waste
Page-based management: The information transmission unit is a fixed-length page, and the physical space of the main memory is also divided into fixed areas of equal length, called pages.
Pros: Much less space wasted
Disadvantages: Not easy to protect, modify, share
Segment page management: Segmentation by module, and paging within the segment, the page is still used as the information transmission unit in and out of the main memory, and the segment table and the page table are used for two-level management.