table of Contents

Wanted to say ...

The protagonist IC: HC595, a little less difficult to analyze, you want to direct this to achieve its internal circuitry, but the frustration some complex logic, so they just realized the function of the IC, there is no point of recovery, but the actual FPGA applications It should be no problem.

IC function first introduced, and then analyze the code complete routine Finally, please read appropriate.

text

IC Introduction _HC595

The HC595 devices contain an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.

The HC595 is taken from this brief description of the data sheet can roughly understand its function.

Actual use, the internal work process:

SRCLK rising edge, SER is input to a first bit shift register (Shift register), the arrival of the rising edge of the second SRCLK value of the first bit shift register shifts to the second bit shift register, while the input timing SER to the first bit shift register, and so on, until the shift register has eight data, QH 'serial output value of the eighth bit shift register (QH' is not able to control the output enable signal, output will have a value of eight bit shift register). Further, when the arrival of the rising edge of RCLK, the value of the shift register is simultaneously being assigned to the storage registers, QA ~ QH output value will be stored in parallel registers, when an output enable terminal is high, the parallel output is high impedance.

SRCLR port shift register clear signal, active low, the value of the shift register will be set to zero.

FIG circuit connection

FIG logic

Code

Next, using Verilog implementing logical functions of the IC, IC programming ideas from functional analysis section herein, in English writing the code readability and aesthetic, inline code.

/*
*作者:方清欢
*日期:2019.11.13
*功能:通过Verilog实现HC595
*备注:本代码仅关注并实现芯片宏观功能,并非针对其内部电路进行代码重现
*/

module HC595
(input SER//Serial data input
,input SRCLK//Serial data input clock
,input RCLK//Storage clock, which may be different from the SRCLK
,input _SRCLR//Shift register data clear
,input _OE//Output-enable
,output reg[7:0]Qp//Parallel data output
,output reg Qs//Serial data output
);
reg[7:0]sft=8'b0;//Shift register
always@(posedge SRCLK)
    if(_SRCLR)
        sft<=8'b0;
    else begin
        sft[0]<=SER;
        sft<=sft<<1'b1;
    end
always@(posedge RCLK)
    if(_OE)begin
        Qp<=8'bzzzz_zzzz;//Qs won't be affected by the _OE
    end
    else begin
        Qp<=sft;
        Qs<=sft[7];
    end
endmodule

This concludes the paper.

I Caishuxueqian, articles or flawed, if you have doubts or different opinions are welcome in the comments area to discuss and improve this article together.

This article belongs to the author and blog Park total, learning to use for reference only, please indicate the source.

This work is Creative Commons Attribution - NonCommercial - ShareAlike 4.0 International License Agreement for licensing.

[FPGA] Verilog 8 bits of serial to parallel converter HC595