FPGA design template sharing (2)--verilog common template sharing

FPGA engineers know that most Verilog codes are always statements, and the structure is basically the same. In order to reduce repetitive work and allow engineers to focus on design and implementation, Mingdeyang has carefully crafted common templates, as long as you install them well GVIM provided by Minde Young can use these templates.

1. Template of sequential logic Enter "Module"
in GVIM and press Enter, as shown in the figure below,



you can get the following sequential logic template.



The template of the module includes a list of input and output signals, signal definitions, combinational logic and sequential logic, etc., which are commonly used components of a module. Students only need to understand the meaning of each part and fill in the blanks as required, there is absolutely no need to memorize them. I see that many students spend a lot of time memorizing and memorizing modules when they first start learning, which is meaningless.

2. Type "Reg" and press Enter.



You can get a single-bit reg signal definition




3. Enter "Reg2" and press Enter



to get a 2-bit reg signal definition




4. Enter "Reg8" and press Enter



to get an 8-bit reg signal definition




Similar shortcut commands are :




To use the above shortcut commands, you need Mingdeyang's configuration file, please follow Mingdeyang's public account "fpga520", or ask for it in the group 97925396. Slogan: Use multiple templates, reduce memory, and focus on design.