Background: In FPGA applications, there is often a situation where we need to send some data from the PC to the FPGA. These data can be used as debug parameters, or some instructions for controlling the FPGA, or as data for calculations.
1: Baud rate: In order to transmit data through the uart protocol, the first thing to determine is the baud rate. The baud rate is the number of bits transmitted per unit time. Common baud rates are 9600, 19200, 38400 and so on. Under normal circumstances, the PC side and FPGA side must ensure that the baud rate received and sent is the same to transmit data correctly, and only when the baud rate is determined can we determine the maximum value of the bit counter.
2: uart protocol sequence: uart protocol includes two data lines, rx line (receiving data line) and tx line (sending data line). Idle state is high level, the start bit is to pull the level low (occupy one bit), followed by eight bits of data bits (here it should be noted that uart transmits low data first), and the end bit pulls the level high. (Accounting for one bit). (It can also occupy a bit position before the end bit to indicate the check bit, but it is generally not used in practical applications)
3: Send data through the serial port assistant: If you send data in the form of a file, the default is to send it in the form of ASCII code, so if we want to manipulate these numbers in the FPGA, we need to decode
By grabbing signal_tap, we can see that the data is correct.
Send the data back to the PC through the tx line again. You can also see that the data is correct.
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