Verilator 4.026 released.
Verilator Verilog HDL simulator is a high-performance system with lint, it does not simply convert Verilog HDL to C ++ or SystemC. Verilator not simply convert Verilog HDL to C ++ or SystemC. Verilator not only translation can also be optimized for the faster model with optional thread partitioning code is compiled, and these models are encapsulated in C ++ / SystemC / Python module.
After Verilog model compiled, even if the speed of the single thread executing on separate SystemC faster than 10 times, and the single thread execution speed 100 times faster than interpreted as Verilog Icarus Verilog simulator or the like. Multithreading may also make 2-10 times faster (on a total of interpretive simulator can improve 200-1000 times).
This updated version includes:
- There are Docker image
- Support bounded queue
- Assertion supported implication operator "| ->"
- Support for string comparison, ato * and other methods
- Supports instant coverage statement
- Update FST tracking API, for better performance
- VpiTimeUnit added and allowed time specified as a string
- Add more concise error in the source code version control conflicts
- Repair little endian byte range
- Repair queue question
- Repair the shell #! Problems caused
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