Verilog HDL syntax (two)
Common mistakes: undeclared register variables
Verilog does not have a mechanism for handling undeclared register variables, so an undeclared identifier is referred to as the default type wire net (such as wire). Assigning a value to a procedure that does not declare a variable will cause a compiler error.
Addressing of wire mesh and register variables
The most significant bit of the part-select of the wire net and register refers to the leftmost array subscript, and the least significant bit is the rightmost array subscript. The expression of a constant or variable can be a subscript of an excerpt. If the subscript of a part-select exceeds its limit, then the reference value of the variable returns a value x.
Example: If an 8-bit word vect_word has a decimal value of 4, then the value of vect_word[2] is 1, the value of vect_word[3:0] is 4, the value of vect_word[5:1] is 2, and vect_word[ 7:0] = 0000_0100, and vect_word[5:1] = 0_0010.
Common mistakes: passing variables through ports
The table summarizes the specifications of the wire mesh type and register variables applied on the Verilog module port. For example, register-type variables cannot be defined on the ***inout*** port.
| Port mode | |||
|---|---|---|---|
| Variable type | input | output | inout |
| Wire mesh variable | Yes | Yes | Yes |
| Register variable | No | Yes | No |
A variable defined as the ***input*** port of the module means that it is a wire mesh variable in the module domain, but the variable defined on the ***output*** port can be hi a wire mesh variable or register variable. Variables defined on the ***input*** port of the module cannot be declared as register variables. The ***inout*** port of the module is not a register type either. The register variable cannot be placed on the output port of the primitive, and it cannot be used as the LHS + variable + assigned object of the continuous copy statement.
Array
A one-dimensional array of reg type is called a memory and represents an array of words. This structure is an extension of register variable declarations to provide memory, such as multiple addressable units with the same word length. An example of the syntax of register variable memory is given below. Non-selection and part-select are Wu Xiaodong for a memory. The smallest unit for buffering the memory is a word. The MSB of the part-select is the subscript of the leftmost array element, and the LSB is on the far right. If a subscript exceeds its convenience, the result should be the logical value x. A constant expression can be used to represent the LSB and MSB in the array definition.
Example: The following code segment shows how to use the simplified form of reg word_size array_name memory_size to define an array of 1024 32-bit ***reg*** type memory variables.
It is also possible to construct a multidimensional array by adding one or more address ranges to the declaration (which provides the type, size, and name).
Example:
reg [15:0] data [0:127][0:127]
If the selected range is a continuous range, Verilog 1995 allows partial selection from the continuous bits of the vector. Verilog 2001 and 2005 provide two additional excerpt operations, which can provide an indicative and variable fixed-width excerpt, +: and -:, the syntax is [<start_bit> +:, <width>] and [< start_bit>-:, <width>]. The parameter width specifies the rightmost or leftmost bit of the vector to be selected. As for the rightmost or the leftmost bit, this depends on the choice of + or -;
Variable working domain
The working domain of a variable is the inside of the module, task, function, or named program block (begin...end) in which it is declared. In the figure below, a wire net of the input port in the child_module can be driven by a wire net and register encapsulated in the parent module parent_module, while the wire net or register on the output port in the child_module can drive the wire net in parent_moudle .
String
For strings, Verilog does not have a separate data type. A character string must be stored in a register of appropriate size through a procedure assignment statement. An appropriate size ***reg*** (array) reserves 8 bits of storage space for each character of the string to be saved.
Example: A ***reg* statement, string_holder , uses num_char to adjust the size of the string;
reg [8*num_char-1:0] string_holder;
The declaration in this example indicates that each character in the num_char character is encoded with 8 bits. If the string "Hello Word" is assigned to string_holder , then num_char is at least 11 to ensure that at least 88 bits can be stored. If the value assigned to an array is less than the number of characters in the array to be processed, then the unused position is automatically filled with 0 starting from the highest bit (for example, the leftmost position).
constant
Constants in Verilog can be declared with the keyword parameter , and the colleague who declares can also assign constants. The value of a constant is constant during the simulation. Constant expressions can be used to declare a constant value.
parameter high_index = 31; // integer
parameter width = 32, depth = 1024; // integers
parameter byte_size = 8, byte_max = byte_size - 1; // integer
parameter a_real_value = 6.22; // real
parameter av_delay = (min_delay + max_delay)/2; // real
parameter initial_state = 8'b1001_0110; // reg
Wire net type and register type reference array
A net or register can be referenced by its identifier. A loud reference can consist of a single bit (for example, a bit or element) or an excerpt of consecutive bits enclosed by square brackets (for example, [7:0]). An expression can be a subscript of an excerpt. If a declared vector identifier has ascending (descending) order from LSB to MSB, then the excerpt referenced by the identifier must have the same ascending (descending) order from LSB to MSB.
reference
"Verilog HDL Digital Design and Synthesis (Second Edition)"