HDL Overview
With the development of EDA technology, using hardware language design PLD / FPGA become a trend. At present the main hardware description language VHDL and verilog HDL and System Verilog. VHDL development of earlier, strict grammar; and Verilog HDL are developed on the basis of the C language on a piece of hardware description language, grammar freer; System Verilog Verilog HDL can be seen as an upgraded version, she is closer to the C language and support multidimensional arrays. Compared to both VHDL and Verilog HDL, VHDL writing rules and grammar is very strict requirements, such as not allowed between different data types assigned to one another and need to be converted, beginners to write non-standard code that the compiler will complain in general; while Verilog is more flexible, integrated and flexible at certain times of the results may not programmers desired result. System Verilog because the information is not a lot of people currently know less. According to the survey using Verilog HDL in our company than the company's use of VHDL. From the point of view of the development of EDA technology, has a hardware C compiler software for CPLD / FPGA design, though not mature, very few applications, but it could become after VHDL and Verilog, designing large-scale CPLD / FPGA yet another means.
Select VHDL or verilog HDL or System Verilog?
This is the most common problem of a beginner. In fact, the difference between these three languages is not large, their descriptive power is similar. To master one of the languages in the future, may be short-term learning fast to learn another language, learn to master the verilog HDL System Verilog is even more simple. What language selection mainly depends on the surrounding population's habits, so you can exchange for future study. Of course, if you are a designer of integrated circuits (ASIC), you must first grasp verilog, because in the IC design field, more than 90% of companies are using verilog the IC design. For PLD / FPGA designers, three languages are free to choose. If you are familiar with C language, it is recommended that you learn verilog HDL, you will find many of the same keywords and syntax of verilog HDL and C language that enables you to quickly break through the language barrier, Quick Start.
A few important tips to learn of HDL
1. Understand the problem of HDL can be integrated:
HDL has two purposes: system simulation and hardware implementation. If the program is only for simulation, then almost all of the syntax and programming methods can be used. But if our program is a hardware implementation (for example: for FPGA design), then we must ensure that the program "synthesizable" (functions of the program can be implemented in hardware circuitry). Non-HDL comprehensive statement will be ignored or an error in the software synthesis. We should bear in mind one thing: "All the HDL description can be used for simulation, but not all of the HDL description can be implemented in hardware."
2. hardware circuit design written in HDL:
HDL is the key to learning to fully understand the relationship between HDL statements and hardware circuitry. Write HDL, a circuit is described later, we finished a program should have some general knowledge of the circuit generated, rather than using pure software design ideas to write hardware description language. To do this, we need more practice, more thinking, more summary.
3. The syntax of your master in the fine, not more
20% of the basic HDL statement can be completed more than 80% of the circuit design, 30% of basic HDL statement can be completed more than 95% of the circuit design, many rare statements are not to be all comprehensive software support in porting or when replacing software platform, prone to compatibility problems, is not conducive to others to read and modify. Recommend common statement more carefully study and understand the meaning of these statements of hardware, a little more than a few new master grammar have used more.
The relationship between HDL and schematic entry method
The traditional relationship between HDL and schematic entry method is like the relationship between high-level language and assembly language. HDL portability, easy to use, but the efficiency is not as good as the schematic; controllability schematic capture a good, efficient, relatively straightforward, but the design of large-scale CPLD / is very cumbersome when FPGA, poor portability. In true PLD / FPGA design, usually recommended schematic and HDL binding method designed for use with a place on the schematic diagram for local use on HDL and HDL, and there is no mandatory requirement. In the shortest possible time, with their most familiar tools to design efficient, stable and meet the design requirements of the circuit is our ultimate goal.
HDL development process
With complete process VHDL / VerilogHD language development PLD / FPGA is:
1. Text Editor: can be carried out using any text editor, HDL can also use a dedicated editing environment. Save the file as .vhd file is usually VHDL, Verilog save the file as .v file
2. Functional Simulation: the file transferred to HDL simulation software for functional simulation, logic check function correctly (also known as pre-simulation of a simple design can skip this step only after completing the wiring, timing simulation)
3. Logic synthesis: the source file transferred to logic synthesis software for a comprehensive, connected relationship that is integrated into the language most simple Boolean expressions and signals. EDA logic synthesis software generates industry standard file .edf (edif) of.
4. layout: the wiring .edf file transferred PLD software provided by the manufacturer, that is designed to place a logic / within the FPGA PLD
The timing simulation: need to use precise parameters obtained in the layout, the sequential circuit verification using emulation software. (Also known as post-simulation)
6. Programming Download: After confirming the simulation is correct, download the file to the chip
Generally above process may be in PLD / FPGA manufacturers provide development tools (such as QuartusII, ISP, ISE) completion, but many integrated PLD development software only supports a subset of VHDL / Verilog, which may result in a small number of grammar can not be compiled, if HDL special tools implemented separately, would be better, otherwise so many reasons to sell HDL development tools company dedicated to the absence of the.
