Verilog hdl achieve single-cycle cpu

Reference count set of experimental test instructions - Jane books , add some details.

1. Add bne instruction

Modify ctrl.v


 

 


 

 


 

After modifying mipstestloopjal_sim.asm, mars dump is bnetest.dat

 


 

Modify sccomp_tb

 


 

modelsim compilation, simulation. Signal Add sccomp_tb: u_ctrl -> i_bne, npc, pc

 


 

Visible i_bne control signal is 1, npc becomes 44. Add bne success

2. Add the jr instruction

Look at the format.

 


 

R type instruction.

Therefore, in ctrl.v modified as follows.


 

ctrl.v and two changes

 


 

Then modify the NPC.v. Note that adding parameters and input

 


 

 


 

 

= Reason RD1 visible sccpu.v

 


 

In ctrl_encode_def defined NPC_JR


 

Add parameters .RD1 in sccpu.v


 

Then write test procedures

$ Ra first assigned to 4. This should continue to cycle.

Export test


 

Do not forget to modify sccomp_tb

 


 

1c can be seen from the waveform diagram of PC 4 is set to change. Added successfully

 


 

3. Add JALR

 


 

ctrl.v

 


 

 


 

 


 

 


 

 

JAL R & lt instruction format is  JAL R & lt RS

Save unconditional jump instruction specified by the register rs, and the address of the next instruction in register $ ra

Test code

 


 

14 seen from the jump 4,


 

And $ ra record 18

 


 

4. Add instruction NOR

 


 

 


 

 


 

In the alu.v

 


 

Test code


 

Waveform:

 


 

register:


 

5. Add instruction sll & sra & srl

Note that this extension done


 

Note also modify the width of the input ALUOp


 

Then in ctrl.v

Write register

Note that only changed RegWrite, RD did not change following


 

 

Add Output

 


 

 

 


 

 

In the sccpu.v


 

 


 

 

 


 

 


 

Test code:

 


 

Waveform: see ALUop correspond sll, srl, sra's 1000,1001,1010

 


 

Register value:

 


 

6.sllv and srlv

 

Here sllv using rs lower five  write himself fifth stage of the CPU (3) - Logic MIPS instruction set, shift and space command - yxwkaifa - blog Park

sllv $t1,$t2,$t3。

则t1值为t2左移t3的低五位

但是这里不太懂,没搞明白是怎么实现的逻辑左右移,位数可变

这里犯了一次错误。复制粘贴后忘了改数字了


 

 


 

 

 


 

 


 

 


 

测试代码:

 


 

波形:

 


 

寄存器变化

 


 

7.stli指令

小于则置一

 


 

 


 

 


 

 


 

测试代码:

 


 

波形:

 


 

寄存器值:

 


 

8.lui指令

取高十六位


 

 


 

 


 

 

 


 

 


 

 

测试代码:


 

波形图:

 


 

寄存器值:

 


 

9.andi指令

 


 

 


 

别忘了RT


 

 

aluop同and


 

测试代码:

 


 

波形图:

 


 

寄存器:

 


 

以上。nice!

学号后八位排序

01510029

lui 0x0151

ori 0x0029

 


 

记得改sccomp_tb

 


 

跑完看result.txt

 


 

大概是完成了排序。

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Origin www.cnblogs.com/lqerio/p/11117623.html