A. Preparations
Look at the reading ( "Computer theory and design Verilog HDL version"), get to know a little principle. Then follow the code book to write about (with 8.4 on it, not 8.6).
Note mux2x32, mux4, cla32 like may be a single cycle mux, alu. (Cla32 is adders)
Then came dffe32 book chapters there.
pipeimem im is the instruction memory IM can apply a single cycle.
pipemem data memory, can apply a single cycle dm
regfile can apply a single cycle of RF.
alu alu fully apply the single cycle. pipecu in aluc, rij type wire, and a portion of wreg codes can apply a single cycle. Just a note to adjust, do not write more, write less, resulting in an error. (I made mistakes that, alu functions and pipecu of aluc inconsistent, less write something, resulting in data read have a problem.)
We need to understand the various issues cpu pipeline and Solutions.
Lw instruction read from the memory such as Register, at the stage before the previous push mem (Forward) to id level, so that if the result of the next instruction to use a register, requiring blocking (STALL) of one cycle, or has entered the stage exe the cpu examples in the book can only forward to id level.
Add here that, with the code of 8.4, and then to eliminate the risk control, mars To test file (.asm) in each of the J type instruction plus a nop. This is because see 8.2.2, using techniques delay slot, instruction is a jump type of instruction I, i + 1 is performed anyway. (To advance in the ID stage is determined whether or not to jump), NOP added here, just replace the i + 1.
II. && adjust the interface details of the adjustment
Written the code, modelsim compile successfully. (Or there is a problem, altered, according to the transcript upgrade).
Then start simulation,
simulation failed to improve error loading design.
Cause substantially error loading design: the error module name (as defined and used.), Parameter error (interface error, inconsistent parameters such as sequence parameter inconsistent width)
Note that line to see a lot of say there is no error loading design tips, this is misleading. (Cause I do not see the prompt to change the day, though indeed changing for the better, some of it) do suggest much, but after the start simulation in modelsim transricpt there will be some error tips
Error: (vsim-3043) E:/pipe3/pipelinecomp_tb.v(55): Unresolved reference to 'ID' in U_SCCOMP.U_SCPU.ID.
This prompts the ID do not know what.
Then I looked at pipelinecpu in, pipeid named id_stage, instead of ID. The ID into id_stage get away
Adjust the interface is very difficult (for me). Be careful.
For example clrn and so is the rest, the need to understand the replacement.
Because example embodiment of the top-level still using a single file cycle, comp the cpu module has only one embodiment of aluout, then it can not ealu in accordance with the code in Module1 8.4 cpu, malu, walu three outputs. Which walu, ealu changed wire type. malu renamed aluout, remain as output.
There pipemem (ie DM, data'memory) as in the embodiment of the comp, there is no need to use the same as 8.4 in the module pipelinecpu.
There are many details need to find their own way.
III. Effects
Sorting or student number, it should be a success
Misplaced a map
This is mars setting momeryconfiguration text at address, and then assemble, and then dump the results.
Correct map
First set mars setting momeryconfiguration data at address, assemble, do not run, dump, then the simulation results
Single-cycle time is so set a start forget ...
