Verilog taillights achieve controller-based
First, the definition module
Module has three inputs: RGB three clock, reset, and the state of cars, and six outputs respectively control the right and left (l, r) of the three-color LED cathode
module car_rear_light
( input clk,
input rst,
input [ 3 : 0 ]car_status,
output reg [ 0 : 0 ]l_light_r, //左侧红灯
output reg [ 0 : 0 ]r_light_r, //右侧红灯
output reg [ 0 : 0 ]l_light_g, //左侧绿灯
output reg [ 0 : 0 ]r_light_g, //右侧绿灯
output reg [ 0 : 0 ]l_light_b, //左侧蓝灯
output reg [ 0 : 0 ]r_light_b //右侧蓝灯
);
Because the left and right turn signals are double flash and yellow , so that the left and right two three-color LED of red, green cathode to the unified arrangement l_light, r_light two control variables
Red + Green <= dirty yellow
reg [ 0 : 0 ]l_light;
reg [ 0 : 0 ]r_light;
always @( posedge clk)
begin
l_light_r = l_light;
l_light_g = l_light;
r_light_r = r_light;
r_light_g = r_light;
end
Dividing below 1Hz
Redefining the parameters frequency module, frequency division factor 12M, onboard 12MHz crystal clock divided 1Hz.
wire clk_1Hz;
divide #(.WIDTH( 32 ),.N( 12_000_000 )) u1 ( //分频12MHz到1Hz
.clk (clk),
.rst_n (rst),
.clkout (clk_1Hz)
);
Finally, a description of the logical section
Condition of the car by the DIP switch control:
0001 - straight, no flash
0010 - left, the left flashing lamp
0100-- turn right, the right flash lamp
1000-- fault, double flash
1111-- reversing, two ordinary white lights bright
always @( posedge clk_1Hz)
begin
case (car_status)
4'b0001 : //直行
begin
l_light <= 1 ;
r_light <= 1 ;
l_light_b <= 1 ;
r_light_b <= 1 ;
end
4'b0010 : //左转
begin
l_light <= ~ l_light;
r_light <= 1 ;
l_light_b <= 1 ;
r_light_b <= 1 ;
end
4'b0100 : //右转
begin
l_light <= 1 ;
r_light <= ~ r_light;
l_light_b <= 1 ;
r_light_b <= 1 ;
end
4'b1000 : //双闪
begin
l_light <= ~ l_light;
r_light <= ~ r_light;
l_light_b <= 1 ;
r_light_b <= 1 ;
end
4'b1111 : //倒车
begin
l_light <= 0 ;
r_light <= 0 ;
l_light_b <= 0 ;
r_light_b <= 0 ;
end
default :
begin
l_light <= 1 ;
r_light <= 1 ;
l_light_b <= 1 ;
r_light_b <= 1 ;
end
endcase
end