Verilog HDL Quick Start 1: Basic overview, structure and data types

table of Contents

1. Terminology and overview

Two, Verilog syntax

1. The basic structure of the program

2. Declaration of modules and ports​​

3. Data type​​​​

4. Numerical representation

5. Module instantiation (call)

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1. Terminology and overview

Overview of RTL synthesis and simulation:

Two, Verilog syntax

1. The basic structure of the program

module module name (port list);  

    Port declaration (including input, output, variables, etc.)

    Declaration of variables and signals of this module

    Actual description of circuit function

    Timing parameters

endmodule

Sample program:

2. Declaration of modules and ports

3. Data type

4. Numerical representation

5. Module instantiation (call)