I2C
I2C bus (Inter-Integrated Circuit), a simple, bidirectional two-wire synchronous serial bus developed by Philips. It only requires two wires to transfer information between devices connected to the bus. Commonly used for the connection between microcontrollers and peripherals.
Hardware connection
I2C only needs two wires to support a master multi-slave or multi-master connection:
- SDA (Serial Data Line): Serial data line.
- SCL (Serial Clock Line): Serial clock line.
letter of agreement
I2C is a serial transmission bus. The transmission is based on 8-bit data transmission. The highest bit (MSB) is transmitted first. After the main chip sends a start signal, it then sends 9 clocks to transmit data.
- Start signal (S): When SCL is high level, SDA high level transitions to low level and starts to transfer data.
- End signal (P): When SCL is at the level, sDA transitions from low to high level, ending the data transfer.
- Response signal (ACK): Every time the transmitter sends a byte, the data line SDA will be released during the ninth pulse of the clock pulse, and then the receiver will feed back a response signal to the transmitter if the response signal is low , It is a valid response bit (ACK for short), indicating that the receiver has successfully received this byte; if this response signal is high, it is a non-acknowledge bit (NACK), generally indicating that the receiver has not succeeded Accept this byte. Specifically, the requirement for the effective acknowledgement bit (ACK) returned is: the receiver pulls SDA low during the low period before the 9th clock pulse, and ensures that it is stable during the high period of the clock Low level. If the receiver is the master, after the last byte he received, it sends a NACK signal to notify the controlled transmitter to end the data transmission and release the SDA line so that the master receiver sends a stop signal P.
The data transmitted on SDA must be stable during the period when SCL is high, and the data on SDA can only change during the period when SCL is low. As shown in the figure: the main chip has to send a start signal at the beginning of the
write operation
, and then send a device address (used to determine which chip to write data), direction (read / write, 0 means write, 1 means read). Response (used to determine whether this device exists), and then you can transfer data, after the data is transmitted, there must be a response signal (to determine whether the data is accepted), and then transmit the next data. Each time a data is transmitted, the receiver will have a response signal, after the data is sent, the main chip will send a stop signal. At the beginning of the
read operation,
the main chip sends a start signal, and then sends a device address (used to determine which chip to read data from), direction (read / write, 0 means write, 1 means read). Response (used to determine whether the device exists), and then you can transfer data, after the data is transmitted, there must be a response signal (to determine whether the data is accepted), and then transmit the next data. Each time a data is transmitted, the receiver will have a response signal, after the data is sent, the main chip will send a stop signal.
Bus speed
Bidirectional transmission bus:
- Standard mode (Standard-mode): rate up to 100 Kbit / s
- Fast mode (Fast-mode): rate up to 400 Kbit / s
- Fast mode + (Fast-mode Plus): The rate is up to 1 Mbit / s.
- High-speed mode (High-speed mode): rate up to 3.4 Mbit / s
Unidirectional transmission bus:
- Ultra Fast-mode: rate up to 5 Mbit / s
