Editor:
. 1, the I2C bus of (a) --- Overview https://www.cnblogs.com/BitArt/archive/2013/05/27/3101037.html
2, the I2C bus of (b) --- Timing https://www.cnblogs.com/BitArt/archive/2013/05/28/3103917.html
3, the I2C bus of the (three) --- C language to understand the IIC https://www.cnblogs.com/BitArt/archive/2013/06/01/3112042.html
-
Overview:
I²C is an abbreviation of the Inter-Integrated Circuit, pronounced "eye-squared cee" or "eye-two-cee", which is a two-wire interface.
I²C bidirectional but with two lines, one Serial Data Line (SDA), another Serial Clock (SCL).
SCL: the rising edge of the data input to each EEPROM device; EEPROM device driver falling output data. (Edge-triggered)
SDA: bidirectional data line for OD door, and any other number of OD and OC gate to "line" relationship.
-
The output stage
Each internal device bus I2C SDA, SCL pin is the same circuit configuration, the output pin and an input buffer driven together. Wherein the output is open-drain FET, with the input buffer phase is a high input impedance, this circuit has two characteristics:
1) Since the SDA, SCL open-drain structure (the OD), they must have pull-up resistors size often 1k8, 4k7 and 10k, but the best performance when 1k8; when the bus is idle, the two lines are high. Any device connected to a low level output on the bus, the bus will make the signal becomes low, i.e., SDA and SCL lines of each device is the relationship "and."
2) pin while the output signal level on the pin will be detected, detects whether the output is consistent with earlier, the "clock synchronization" and "bus arbitration" hardware basis.
-
Master and slave devices
All peripheral devices in the system has a 7-bit "address from the device-specific code", wherein the height of the device 4 type, developed by the manufacturer, the lower three bits defining the address pins of the device, defined by the user. Master device multiprocessor communication mechanisms by address code, thus eliminating the I2C bus chip select line of peripheral devices, so that no matter how many devices present on the bus, the system still simple wire structure. A terminal mounted on the bus, from the main side and the sub side, the master must be a logic module with the CPU, on the same bus at the same time enabling a master terminal, there may be a plurality of ends from the number from the end of by address space and maximum capacitance limit of 400pF bus.
-
- The main drive for the master SCL line;
- Generating in response to the master device from the device;
Both can transmit data, but can not initiate a transmission from the equipment, and the transmission is controlled by the master device.
4. Rate:
Normal mode: 100kHz;
Fast mode: 400kHz;
High-speed mode: 3.4MHz;
There is no need to use high-speed SCL, SCL will remain at or below 100k, then forget it.
The I2C bus (B) --- Timing
A protocol 1. Idle state when the bus I2C bus SDA and SCL at high level while the two signal lines, defined as the bus idle state. At this time, the output of each stage FET devices are in the OFF state, i.e., the bus is released by the two signal lines of each of the pull-up resistor deasserted. 2. The start and stop bits definition:
- Start signal: the period when the SCL is high, from high to low transition of the SDA; activation signal is a level transition timing signal, rather than a signal level.
- Stop signal: the period when the SCL is high, the SDA transition from the high to low; stop signal level transitions is also a timing signal, rather than a signal level.
3.ACK
Each transmitter transmits a byte, it releases the data line during a clock pulse 9 by a receiver feedback response signal. Response signal is low, a valid response to a predetermined bit (ACK acknowledge bit for short), indicates that the receiver has successfully received the byte; response signal is high, a predetermined non-acknowledge bit (NACK), reception generally represents this byte is not received successfully. For effective feedback ACK bit requirement is low before the receiver during the 9th clock pulse the SDA line low, and to ensure a high level during the low level of the clock is stable. If the receiver is master, then after it receives the last byte, transmitting a NACK signal to inform him of the transmitter end of the data transmission, and releases the SDA line to the master receiver sends a stop signal P.
FIG sampling results following logic analyzer: After releasing the bus, if no response signal, SDA should be continued at a high level, but the blue dotted line shown in part, which is pulled down to a low level, the received proof the response signal. This gives us the inside information are two: 1) Receiver to pull the SDA during the low period before the arrival of the rising edge of SCL; 2) the response signal is maintained until the end of the falling edge of SCL; As previously noted red logo that.
4. The validity of data:
The I2C bus data transfer, the clock signal is at high level, the data line must be stable, only the signal of the clock line is low only during the high or low state of the data line allowed to change. I understand: Although only required to maintain stable during the high period, but to have an advance, that is, data before the arrival of the rising edge of SCL would need to be ready, because in front of an overview of the I2C bus (a) --- the article has been pointed out, the data is driven into the rising edge of SCL device (EEPROM) in.
5. Data transfer:
Every data transfer on the I2C bus has a corresponding clock pulse (or synchronization control), i.e., in cooperation with the serial clock SCL, bit by bit per bit serial data on SDA. Of the data bits are edge-triggered.
Second, the work process
All communication on the bus are initiated by the master. In a communication, the master and slave are always in play two different roles.
1. The data transmitted from the master device to the device
The master sends a start bit, which will inform the transmission of all devices on the bus started, the host sends the next device address matches the address of the slave will continue this transfer process, while the other slave will ignore the next transmission and waiting for the next transmission begins. From the master device addressed to the device, it transmits it to read or write from the internal device register address; after the transmission data. After the data has been sent, transmission stop bits:
Write process is as follows:
Sending the start
- Sent from the device address and the read / write select bit; release bus, until a response bus EEPROM down; EEPROM If reception is successful, it responds; EEPROM no answer or if no negotiation is successful data transmission errors, which requires that or terminate the retransmission.
- Send internal register address you want to write; EEPROM response to their issue;
- send data
- Stop bit.
- EEPROM after receipt of the stop signal goes to the inside of a writing period takes about 10ms, the operation will not be here any response EEPROM; (and therefore in this manner twice to insert a delay between the write, or will result in failure, bloggers were here in the pits for a moment)
detailed:
Note: ① the master establish communication by transmitting the address code corresponding to the controller, and on the bus while the other controller is also received address code, but because of its own address does not consistent, so quit communicating with the master in advance;
2. master reading data process:
Read more complex process, in the former slave read data from, you must first tell it which is what you want to read internal registers, and therefore must be written (dummy write):
-
Start bit is sent;
-
Transmitting slave address + write bit set;
-
Transmitting the internal register address;
-
Re-transmitting the start bit, i.e., the restart;
-
Resend slave address + read bit set;
-
Read data
Master receiver after receiving the last byte, the ACK signal is not issued. Thus, the slave releases the SDA line transmitter to allow the end of the transmission signal sent by the host P.
-
Send stop bit
detailed:
The I2C bus (C) --- C language to understand the IIC
In order to deepen the understanding of the I2C bus, the C language simulation IIC bus watching read waveform source side:
As shown below in the timing chart of a write operation:
Read Timing understanding empathy. For friends do not understand the timing refer to " the I2C bus of the (two) --- Timing "
Complete program as follows:
#include<reg51.h>
#define uchar unsigned char
#define uint unsigned int
#define write_ADD 0xa0
#define read_ADD 0xa1
uchar a;
sbit SDA=P2^0;
sbit SCL=P2^1;
void SomeNop(); //短延时
void init(); //初始化
void check_ACK(void)；
void I2CStart(void);
void I2cStop(void);
void write_byte(uchar dat);//写字节
void delay(uint z);
uchar read_byte(); //读字节
void write(uchar addr,uchar dat); //指定地址写
uchar read(uchar addr); //指定地址读
bit flag; //应答标志位
void main()
{
init();
write_add(5,0xaa); //向地址5写入0xaa
delay(10); //延时,否则被坑呀！！！
P1=read_add(5); //读取地址5的值
while(1);
}
//***************************************************************************
void delay()//简单延时函数
{ ;; }
//***************************************************************************
void start() //开始信号 SCL在高电平期间，SDA一个下降沿则表示启动信号
{
sda=1; //释放SDA总线
delay();
scl=1;
delay();
sda=0;
delay();
}
//***************************************************************************
void stop() //停止 SCL在高电平期间，SDA一个上升沿则表示停止信号
{
sda=0;
delay();
scl=1;
delay();
sda=1;
delay();
}
//***************************************************************************
void respons() //应答 SCL在高电平期间，SDA被从设备拉为低电平表示应答
{
uchar i;
scl=1;
delay();
//至多等待250个CPU时钟周期
while((sda==1)&&(i<250))i++;
scl=0;
delay();
}
//***************************************************************************
void init()//总线初始化 将总线都拉高一释放总线 发送启动信号前，要先初始化总线。即总有检测到总线空闲才开始发送启动信号
{
sda=1;
delay();
scl=1;
delay();
}
//***************************************************************************
void write_byte(uchar date) //写一个字节
{
uchar i,temp;
temp=date;
for(i=0;i<8;i++)
{
temp=temp<<1;
scl=0;//拉低SCL，因为只有在时钟信号为低电平期间按数据线上的高低电平状态才允许变化；并在此时和上一个循环的scl=1一起形成一个上升沿
delay();
sda=CY;
delay();
scl=1;//拉高SCL，此时SDA上的数据稳定
delay();
}
scl=0;//拉低SCL，为下次数据传输做好准备
delay();
sda=1;//释放SDA总线，接下来由从设备控制，比如从设备接收完数据后，在SCL为高时，拉低SDA作为应答信号
delay();
}
//***************************************************************************
uchar read_byte()//读一个字节
{
uchar i,k;
scl=0;
delay();
sda=1;
delay();
for(i=0;i<8;i++)
{
scl=1;//上升沿时，IIC设备将数据放在sda线上，并在高电平期间数据已经稳定，可以接收啦
delay();
k=(k<<1)|sda;
scl=0;//拉低SCL，使发送端可以把数据放在SDA上
delay();
}
return k;
}
//***************************************************************************
void write_add(uchar address,uchar date)//任意地址写一个字节
{
start();//启动
write_byte(0xa0);//发送从设备地址
respons();//等待从设备的响应
write_byte(address);//发出芯片内地址
respons();//等待从设备的响应
write_byte(date);//发送数据
respons();//等待从设备的响应
stop();//停止
}
//***************************************************************************
uchar read_add(uchar address)//读取一个字节
{
uchar date;
start();//启动
write_byte(0xa0);//发送发送从设备地址 写操作
respons();//等待从设备的响应
write_byte(address);//发送芯片内地址
respons();//等待从设备的响应
start();//启动
write_byte(0xa1);//发送发送从设备地址 读操作
respons();//等待从设备的响应
date=read_byte();//获取数据
stop();//停止
return date;//返回数据
}
