[STM32] Detailed I2C

00. Table of Contents

Article Directory

01. Introduction to I2C

The I2C (Inter-Integrated Circuit) bus interface is used as the interface between the microcontroller and the I2C serial bus. It provides a multi-master mode function that can control all I2C bus specific sequences, protocols, arbitration and timing. It supports standard and fast modes. It is also compatible with SMBus 2.0.

It can be used for many purposes, including CRC generation and verification, SMBus (system management bus), and PMBus (power management bus).

Depending on the device, the DMA function can be used to reduce the workload of the CPU.

02. I2C main features

Parallel bus/I 2 C protocol converter
● Multi-master mode function: the same interface can be used as both master mode and slave mode
● I 2 C master mode characteristics:
— Clock generation
— Start bit and stop bit generation
● I 2 C Slave mode features:
— Programmable I 2 C address detection
— Double addressing mode, which can respond to 2 slave addresses
— Stop bit detection
● 7-bit/10-bit addressing and general call generation and detection
● Supports different communications Speed:
— Standard speed (up to 100 kHz)
— Fast speed (up to 400 kHz)
● Programmable digital noise filter for STM32F42xxx and STM32F43xxx
● Status flag:
— Transmit/receive mode flag
— Byte transfer end flag
— I 2 C Busy flag
● Error flag:
— Loss of arbitration in master mode
— Response failure after address/data transfer
— Detection of misplaced start and stop bits
— Prohibition of overflow/underflow after clock extension
● 2 Two interrupt vectors:
— An interrupt is triggered by a successful address/data byte transfer event
— An interrupt is triggered by an error state
● Optional clock extension

● 1-byte buffer with DMA function
● Configurable PEC (Packet Error Check) generation or verification:
— In Tx mode, the PEC value can be transmitted as the last byte
— PEC for the last received byte Error checking
● SMBus 2.0 compatibility:
— 25 ms clock low level timeout delay
— 10 ms master device accumulated clock low level extension time
— 25 ms slave device accumulated clock low level extension time
— hardware PEC generation with ACK control /Verification
— Support Address Resolution Protocol (ARP)
● PMBus compatibility

03. I2C function description

In addition to receiving and sending data, this interface can also convert from serial format to parallel format, and vice versa. Interrupts are enabled or disabled by software. The interface is connected to the I 2 C bus through data pins (SDA) and clock pins (SCL). It can be connected to a standard (up to 100 kHz) or fast (up to 400 kHz) I 2 C bus.

Mode selection

The interface can choose one of the following four modes when working:
● Slave transmitter
● Slave receiver
● Master transmitter
● Master receiver
By default, it works in slave mode. The interface will automatically switch from the slave mode to the master mode after the start bit is generated, and switch from the master mode to the slave mode when the arbitration is lost or the stop bit is generated, thereby realizing the multi-master mode function.

IIC block diagram
Insert picture description here