The I2C interface of FM33A0XX is only used as a master, and does not support multi-master, so other devices hung on the bus are all slaves. The master always provides the synchronous clock SCL on the bus, and the SDA data flow direction can be the master sends the slave to receive, or the slave sends the master to receive.
Data sending process
1. The master initiates START sequence
2. The master sends the slave address. The slave address includes 7 slave addresses and 1 R/W flag. When sending data, the R/W bit is 0.
3. The host sends the first frame of 8-bit data.
4. After the host sends 8-bit data each time, it will judge whether a valid ack is detected at the 9th clock. If the host detects that the
ack is successful, it will continue to output the next set of 8-bit data.
5. If the slave fails to respond to the ack, the master should send a STOP sequence to terminate the transmission after detecting that the ack fails.
Note: The slave address includes 7-bit slave address and 1 R/W flag.
Data receiving process
1. The host initiates the START sequence
2. The host sends the slave address. The slave address includes 7-bit slave address and 1 R/W flag bit. The R/W bit is 1 when data is read.
3. At this time, set SSPCON.RCEN to 1, and the host will automatically turn to the receiving state.
4. The host starts to receive the first frame of 8-bit data, and sends a valid ack to the slave at the 9th clock, so as to continue to read the next frame. 8
bit data.
5. After the host reads, it sends STOP sequence to terminate the read.