Question: As in the question, in addition to the fact that the address is not repeated, I heard that the number of ICs is only limited by the maximum capacitance of the bus line of 400pF, so how to calculate the capacitance?
Answer: The input capacitance of an I2C device pin is 10pF, and then consider the wiring. In
general applications, there is no problem with hanging 3 or 5. Pay attention to address conflicts. Change the pull-up resistance to 2.2k, or even 1k.
Answer: Of course, the more peripherals connected, the greater the parasitic capacitance of the trace. When the capacitance is too large to affect the integrity of the signal, then the signal becomes invalid. No matter how many peripherals are connected, it is useless.
The calculation of this capacitor is basically difficult. It depends on the wiring and board manufacturing process, but you can simulate it on the computer now and get a rough result.
The error of my own calculation must be huge
Answer: Measure the rise and fall time of I2C, Ok is enough
Question: In other words, when more slaves are connected, the pull-up resistance should be relatively reduced, right?
Answer: Every I2C device has parasitic capacitance. Add them up and there are also traces. The capacitance mainly affects the rise and fall time of I2C. You can measure it within the specification range. In addition, reduce the pull-up resistance. The rise time can also be improved, but it should not be too small. Although it is an open drain, the low voltage of I2C will be higher if the resistance is too small. It cannot exceed the specifications, and there is also a large leakage current.
Answer: Positive solution, this is mainly considering the pull-up drive and frequency response issues. There is also the maximum value of the low level. The maximum value of the low level determines the minimum value of the pull-up resistor
Answer: This capacitance value is the capacitance value on the entire I2C communication bus. There are more devices connected in parallel, and the capacitance of each unit needs to be reduced to ensure that the total capacitance value does not exceed the requirement. Otherwise, the rising edge and falling edge time of the I2C waveform will be biased. Long, and there is a large oscillation, resulting in a high bit error rate.
Answer: The bus capacitance Cb is the total capacitance of a bus line connection and pin, and the unit is pF. Due to the specified rise time, this capacitor limits the maximum value of the pull-up resistor Rp, and the power supply voltage limits the minimum value of the pull-up resistor Rp. The minimum pull-down current specified for the output stage at VOLmax=0.4V is 3mA. (VDD-Volmax)/3mA=(3.3V-0.4V)/3mA=0.97kΩ, when the voltage VDD of the pull-up resistor is 3.3V, the pull-up resistor needs at least 0.97K
If the capacitive load of the bus line increases, the bit rate will gradually decrease. When the capacitive load of the bus is 400pF, the maximum bit rate allowed is 1.7Mbit/s. When the bus capacitance load is 100pF~400pF, the timing parameters must increase linearly.