1. Introduction
The I2C (Inter-integrated Circuit) bus supports short-distance communication between devices. It requires two signal lines to complete information exchange (one SDA, serial data line; one SCL, serial clock line). I2C was first developed and designed by Philips in 1982 and used on its own chip. At the beginning, only 100kHz, 7-bit standard addresses were allowed. In 1992, the first public specification of I2C was issued, adding 400kHz fast mode and 10-bit extended address. On the basis of I2C, Intel proposed "System Management Bus" (SMBus) in 1995 for low-speed device communication. SMBus limits the clock frequency to 10kHz 100kHz, but I2C can support 0kHz 5MHz devices: normal mode (100kHz is 100kbps ), Fast mode (400kHz), fast mode + (1MHz), high-speed mode.
Two, I2c agreement
1. Starting conditions
In order to mark the official start of the transmission, the master device will set SCL high (when the bus is idle, SDA and SCL are in a high state), and then pull SDA low, so that all slave devices will know that the transmission is about to start . If both master devices want to take ownership of the bus at the same time, then whoever pulls SDA low will win control of the bus. During the entire communication period, there may be multiple start to start each new communication sequence.
2. Address Frame
Used by the master to indicate to which slave the message is sent.
The address frame always appears at the very beginning of a communication. A 7-bit address is sent from the highest bit (MSB). This address will be followed by a 1-bit operator, with 1 for read operations and 0 for write operations.
The next bit is NACK / ACK. After the first 8 bits in this frame are sent, the receiving device obtains SDA control. At this time, the receiving device should reply an ACK (pull SDA low) before the 9th clock pulse. Indicates that the reception is normal. If the receiving device does not pull SDA low, the receiving device may not have received data (such as the addressed device does not exist or the device is busy) or the received message cannot be parsed. If so, the master will come Decide what to do (stop or repeated start condition).
3. Data Frame
Data sent from master to slave (or slave to master), each frame is 8-bit data.
After the address frame is sent, data transmission can begin. The master continues to generate clock pulses, and the data is placed on the SDA by the master (write operation) or slave (read operation). Each data frame is 8 bits, and the number of data frames can be arbitrary until a stop condition is generated. After each frame of data transmission (that is, every 8-bit), the receiver needs to reply with an ACK or NACK (the slave sends ACK when writing data, and the master sends ACK when reading data. When the master knows that it has finished reading the last byte of data Time, you can send NACK and then stop condition).
4. Stop condition
When all data is sent, the master will generate a stop condition. The stop condition is defined as: when SDA is placed low, SCL is pulled high and held high, and then SDA is pulled high.
Note: During normal data transmission, when SCL is at a high level, the value on SDA should not change to prevent an unexpected stop condition.
5. Repeated start conditions
SDA is pulled high when SCL is low, then SCL is pulled high. Then the master can generate a start condition to continue the new message transmission.
6. Clock stretching, clock synchronization, bus arbitration
Three, I2C read and write process
1. Standard process for writing registers
- Master initiates START
- Master sends I2C addr (7bit) and w operation 0 (1bit), waiting for ACK
- Slave sends ACK
- Master sends reg addr (8bit), waiting for ACK
- Slave sends ACK
- Master sends data (8bit), that is, the data to be written into the register, waiting for ACK
- Slave sends ACK
- Steps 6 and 7 can be repeated multiple times, that is, write multiple registers in sequence
- Master initiates STOP
2. Standard process for reading registers
- Master sends I2C addr (7bit) and w operation 1 (1bit), waiting for ACK
- Slave sends ACK
- Master sends reg addr (8bit), waiting for ACK
- Slave sends ACK
- Master initiates START
- Master sends I2C addr (7bit) and r operation 1 (1bit), waiting for ACK
- Slave sends ACK
- Slave sends data (8bit), the value in the register
- Master sends ACK
- Steps 8 and 9 can be repeated multiple times, that is, reading multiple registers in sequence
