I2C bus
I2C bus (Inter-Integrated Circuit Bus) developed by Philips is a simple, two-wire bidirectional synchronous serial bus. It only requires two wires to transmit information between devices connected to the bus. Some books also written document or IIC, pronounced "I square C".
I2C is one of the most important bus communication protocol embedded in the most common. Many sensors are peripheral chips using the I2C protocol. It has the following characteristics:
(1) simple hardware circuit: I2C bus requires only one data line and one clock line two lines,
(2) flexibility: the address and data transfer settings set by software, very flexible. Devices on the bus added and deleted without affecting other devices work properly.
(3) the number of devices can be connected to: the number of IC is connected to the same bus is limited only by the maximum bus capacitance.
4.8.1 I2C device address
I2C is a bus master, all data transfers must be initiated by the host from the bus structure, typically as the host microcontroller, other devices connected to the I2C bus or device is called a slave.
Another important concept I2C: device address. I2C bus is connected to the device, in addition to the host, each device has its own address. And when a host wants to communicate with the device, the device address is sent first to the I2C bus.
I2C device address is generally eight, the last one is to read and write flag. 0 indicates that the host device to read the data; represents 1 to the host device to write data.
4.8.2 I2C Timing
I2C bus requires only two lines, the clock line (the SCL), a data line (SDA). Wherein the clock line provides a time period, the shorter the period of time the faster data transfer rate. A data line for transmitting the start bit, acknowledge bit, data and the like. As shown in a timing chart 4.37.
4.37 I2C timing chart of FIG.
There are data format start bit, stop bit, data bit, acknowledge bit (ACK), NACK.
1 start bit
When the host wants to initiate I2C data transfer needs to first send the start bit to the I2C bus. Conditions of the start bit is SCL line is high, SDA line is switched from high to low.
2. Stop Bit
When the host wants to terminate the I2C data transmission, we need to send a stop bit I2C bus, I2C bus occupied release. Stop bit that the SCL line is high, SDA line is switched from the low level to the high level.
3. Data bits
Each byte of data SDA line must be 8 bits, the number of bytes per transfer is not limited. After each byte must be followed by one acknowledge bit (ACK). First, transmission data is the most significant bit (the MSB), the data on the SDA must remain stable when the SCL high period, high and low level inversion occurs in the data change SCL low period.
4. Acknowledge bit
Each byte is transmitted with the response bits must, also correlated response generated by the master clock, during clock impulse response (the ninth clock cycle), the sender releases the SDA line, the receiving terminal SDA low.
5. NACK position
The following situations will cause NACK bits:
(1) the address transmitter receiver does not respond, the receiving side transmits ACK to the transmitter no
(2) Since the receiver is busy processing program causes the real-time contact can not receive or send
(3) the transmission process, the receiver can not identify the sender of data or command
(4) The receiver can not receive
(5) After completion of reading the host receives the data, it sends a NACK to inform the slave end
4.8.3 Analog I2C
I2C bus are relatively simple, can according to the I2C timing, using the I / O simulation I2C. This article will use the STM32 I2C GPIO port analog functionality to help readers understand the timing of I2C control.
Open Chapter4 \ 05_I2C_24c02 \ mdk \ IIC24c02.uvproj project file, and then open the file 24c02.c, IIC simulation code in this file.
1. I2C initialization
I2C initialization part of the code is mainly to initialize the STM32 GPIO. GPIOB_9 as a data pin (SDA), GPIOB_8 as a clock pin (SCL), code is as follows:
//Chapter4\05_I2C_24c02\USER\24C02\24c02.c 5 // I2C line initialization IIC_Init void (void) {
GPIO_InitTypeDef GPIO_InitStructure;
RCC_AHB1PeriphClockCmd (RCC_AHB1Periph_GPIOB, the ENABLE); // open GPIOB clock // GPIOB8, B9 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; // output mode GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; // open drain output GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; // 100MHz GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; // pull GPIO_Init (GPIOB, & GPIO_InitStructure); // initialization
IIC_Stop (); // give a stop signal, reset all devices on the bus I2C}
2. The start signal
When the SCL is high, a falling edge of the SDA occurs I2C Bus start signal, as follows:
//Chapter4\05_I2C_24c02\USER\24C02\24c02.c 23 // I2C start signal line IIC_Start void (void) {
// SDA first output pin is set high. 1 = IIC_SDAOUT;
// the SCL pin is set high IIC_SCL = 1 ;
// wait delay_us 4us (. 4);
// = 0 the SDA pin low IIC_SDAOUT;
// wait delay_us 4us (. 4);
// the SCL pin low IIC_SCL = 0; // data is ready to send or receive data}
IIC_SCL refers to the I2C SCL pin, IIC_SDAOUT output I2C SDA pin means and are respectively defined as PBout (8) and PBout (9) in 24c02.h file, as follows:
//Chapter4\05_I2C_24c02\USER\24C02\24c02.h 8行#define IIC_SCL PBout(8) //SCL#define IIC_SDAOUT PBout(9) // SDA
IIC_SDAOUT = 1 indicates SDA pin output high. Here is another way to write GPIO output high and low, it is equivalent to the previous GPIO_WriteBit (GPIOB, GPIO_Pin_9, Bit_SET).
IIC_Start function uses SDA, SCL pin, through the output operation and high and low latency, simulated I2C start signal. 4.38 as shown in FIG its timing.
4.38 I2C start timing signal of FIG.
3. Stop Signal
When the SCL is high, a rising edge appears showing the SDA I2C bus stop signal, as follows:
//Chapter4\05_I2C_24c02\USER\24C02\24c02.c 34 rows IIC_Stop void (void) {
// the SDA to a low level, so as to rising edge = 0 IIC_SDAOUT;
delay_us (. 4);
// the SCL high IIC_SCL . 1 =;
delay_us (. 4);
// the SDA goes high from low, a rising edge appears. =. 1 IIC_SDAOUT;
}
4. The response signal
All data on the I2C bus are transferred in 8-bit bytes, each byte is transmitted the transmitter, in response to the clock pulse period (ninth clock cycle), a feedback response signal by the receiver. Response signal is low, a valid response to a predetermined bit (ACK acknowledge bit for short), indicates that the receiver has successfully received the byte; response signal is high, a predetermined non-acknowledge bit (NACK). Host waits response signal from the relevant machine code is as follows:
Return Value @ row //Chapter4\05_I2C_24c02\USER\24C02\24c02.c 50: 1 indicates NACK, 0 represents MCU_Wait_Ack ACKu8 (void) {
U8 ACK;
IIC_SDAOUT = 1;
delay_us (1);
IIC_SCL = 1;
delay_us ( 1);
// read level SDA bus IF (IIC_SDAIN)
{
ACK = 1; // NACK response indicates a high level}
the else {
ACK = 0; // low level indicates NACK response}
IIC_SCL = 0;
delay_us (. 1);
return ACK;
}
The data bit
Every data transfer on the I2C bus has a corresponding clock pulse. During rendering high SCL, SDA level must remain stable on the low level data 0, data 1 is high. Only the SCL is low, the level is allowed to change the state of the SDA. Level to a low voltage logic 0 and a logic 1 are high level. 4.39 timing shown in FIG.
FIG bit data transmission timing 4.39
6. Send a byte
Write a byte corresponds to I2C bus I2C transmitted 8 data bits, the data transmission timing according to a bitmap 4.39, we can use the I / O simulation, as follows:
//Chapter4\05_I2C_24c02\USER\24C02\24c02.c 113 @ line parameters: void Senddata data to be transmitted IIC_write_OneByte (U8 sendData) {
U8 T;
IIC_SCL = 0;
for (T = 0; T <. 8; T ++)
{
// = the first transmitting high IIC_SDAOUT (sendData & 0x80) >>. 7;
// left = 1 sendData (sendData <<. 1);
delay_us (2);
IIC_SCL =. 1;
delay_us (2);
IIC_SCL = 0;
delay_us ( 2);
}
}
The more the key code is Senddata shift operation.
According to the characteristics >> and &, (Senddata & 0x80) >> 7 corresponds to the highest Senddata reserved, the other bit is cleared, and then move to the right highest lowest level. Corresponds to the highest value assigned Senddata IIC_SDAOUT, to achieve high low output of the SDA pin Senddata The highest response.
After Senddata = (Senddata << 1), the second high sendData left by a manner that the second upper sendData becomes highest.
Through the for loop, which is repeated two steps, the Senddata each bit transmitted. In order to facilitate intuitive understanding, we assume Senddata equal to 170 in hexadecimal: 0xAA, binary is: 10101010. For the whole cyclic shift operation can be represented visual 4.40 FIG.
4.40 shifting operation flowchart of FIG.
7. Read a byte
Read timing and transmission timing of the same, except that the need to change the data bit on SDA while SCL low level when transmitting, the need to read the data bits in the SDA when the SCL high reading. Meanwhile, each bit of data is read, left a need to ensure high byte first. After reading data to send ACK or NACK response signal. Substituting the following:
//Chapter4\05_I2C_24c02\USER\24C02\24c02.c 137行u8 IIC_Read_OneByte(u8 ack){
u8 i,receivedata=0;
for(i=0;i<8;i++ )
{
IIC_SCL=0;
delay_us(2);
IIC_SCL=1;
receivedata<<=1;
if(IIC_SDAIN)
{
receivedata++;
}
delay_us(1);
}
if (!ack)
MCU_NOAck();
else MCU_Send_Ack();
return receivedata;
}
4.8.4 Summary
I2C is the most common embedded bus protocol, readers need to master to understand the timing IIC and can use the I / O simulation I2C operation.