Summary
The I2C bus is a very basic and commonly used bus interface.
Not only that, there are many bus interfaces based on I2C, such as SMBus, IPMI, PMBus, etc.
The I2C bus is physically composed of two wires, a data wire and a clock wire.
Devices connected to the I2C bus include microprocessors, LCDs, LEDs, GPIO, EEPROM, RTC, AD/DA converters, etc. The following is an example:
There are more complex examples, I2C can also be extended through Switch, etc.:
There can be one or more I2C controllers in a general system, and multiple I2C controllers can expand multiple I2C buses without interfering with each other.
Devices on the I2C bus are divided into two types: master and slave. The master device is the device that actively initiates the I2C service. The I2C request method is that the master device initiates data transmission and activates the clock signal to allow this data transmission.
Each I2C device has a unique address (relative to the bus, because there can be multiple I2C buses in a system), and the master device accesses the slave device through the I2C address.
The master and slave devices are not fixed. Some devices can be master or slave. Of course, some devices can only choose one.
The I2C bus also supports multi-master devices, that is, multiple devices can initiate I2C services at the same time.
In the case of multi-master devices, it relies on clock synchronization and arbitration to determine who can gain control of I2C at this moment.
I2C bus protocol
The I2C bus protocol specifies the following:
Therefore, the beginning and end of the I2C business have specifications for data lines and clock lines:
When the business starts, the clock line is pulled high, and the data line falls along.
When the service ends, the clock line is pulled high and the data line rises.
In the middle is the transmission of data.
During data transmission, the clock signal is switched between high and low levels at a fixed frequency. The data line level obtained at high level represents the actual 1 (high level) and 0 (low level). The data line can change data when the clock is pulled low. :
A data transmission contains 8 bits, followed by an ACK bit. The sender releases the data line and waits for the receiver to pull down the data line, indicating that the receiver has successfully received the data, and the sender can continue to transmit the data.
If the data line is not pulled low but remains high, it means NACK, which may be one of the following situations:
- Recipients without data;
- The recipient is busy;
- The recipient receives unrecognized data or commands;
- The recipient did not receive enough data;
- When the master device is the receiver, it needs to send NACK to the sender of the slave device;
When multiple master devices use the I2C bus at the same time, they need to rely on clock synchronization and arbitration, which will not be introduced in detail.
Device access involves addresses. It should be noted that the address is also transmitted on the data line, and it follows the service start signal.
The I2C address has 7-bit and 10-bit situations. It should be noted that the previous I2C data transmission and reception was 8 bytes, so the transmission of the 7-bit address signal requires 1 byte, and the 10-bit address signal 2 bytes are required for transmission.
Immediately after the address is the read and write bit, which indicates the operating direction of the master device. The following is an example of a 7-bit address:
The following is an example of a 10-bit address:
The following is a complete data transfer:
Some I2C addresses are reserved, they have special uses, as shown below:
The general call address indicates that it is sent to all devices on the I2C bus.
If these devices do not need data, they do not send an ACK signal, otherwise they send an ACK and act as a slave.
If you send a 06h after sending the general call, it means that the device on the I2C bus is soft reset (some devices do not have this function, then there is no need to reset).
Device ID is used to obtain I2C device information, the specific format is as follows:
Bus speed
The speed of I2C data transmission is 100kbit/s by default, and can be set to different values later:
Normally, the speed of I2C is very slow compared to the CPU, even in terms of its maximum speed.
And sometimes because of the hardware signal, if the set speed is higher, it will cause abnormal data transmission.
Implementation of I2C Bus on Hardware Platform
The I2C bus is just two wires.
Generally, there is a default I2C controller in the system, and the software needs to operate the controller registers.
In addition, I2C can also be simulated through GPIO. At this time, software is required to operate the relevant level through GPIO to realize the I2C bus function.
Take the Intel PCH model Z370 as an example, which contains the following I2C controller:
You can also see from here that they are multiplexed with GPIO, so you can also configure it as GPIO, and then implement I2C by yourself, but it seems that there is no special need.
There is no register description of the I2C controller that can be referred to, so the specific software operation mode is omitted.
Visual I2C transmission
The transmission speed of I2C is very slow, so it is convenient to check the specific data transmission through external tools.
For example, connect the oscilloscope to the data and clock lines to view all the data.
In addition, there are special tools to connect to the I2C bus, and then connect the other end to the computer, and use the tools on the computer to read I2C services, such as the following tools:
Using such a tool can easily locate I2C bus-related problems.
reference
《I2C-bus specification and user manual.pdf》
《200-series-chipset-pch-datasheet-vol-1.pdf》