I2C Bus (based IMX6ULL description)

I2C (Inter-Integrated Circuit BUS) is I2C BUS short, Chinese integrated circuit bus, is one of the most widely used buses, and some related IMX6ULL that happens is that the bus design PHILIPS NXP predecessor. Currently it remains one of the most widely used bus protocol.

1 General Introduction I2C protocol

1) Overview of
I2C is a serial communication bus, multi master-slave architecture, in order to allow the original designer motherboards, embedded systems or mobile phones to connect low speed peripherals and evolved. Small amount of data occasions, short transmission distance, at any moment, only one host and other characteristics. Strictly speaking, I2C should be a combination of hardware and software, so we will be divided into physical layer and protocol layer to introduce the bus. (Bus structure below)

2) physical layer
characteristics of the 1: half (non-full duplex)
two bus lines:
SDA (serial data line): a master chip via the SDA line can send data to the device from both It can also be read from the data SDA, which connecting pins SDA line must have two pins (pin transmitting / receiving pin), end device specific reference I2Cn_SDA (output / input) at FIG.
SCL (serial clock line): consistent with the structure with the SDA pin, the pin and the output drive input buffer together. Wherein the output is open-drain FET, an input buffer with high input impedance of the phase. Such configuration has the following features:
Ø due SDA, SCL are open-drain, by means of an external pull-up resistor on the signal "line and the" logic;
Ø pin while the output signal level on the pin will testing, test whether the output just the same. Provide hardware foundation for the "clock synchronization" and "bus arbitration."
SDA and CLK line connecting the two pull-up resistor is connected, when the bus is idle, two lines are high. Any device connected to a low level output on the bus, the bus will make signal goes low. (Physical layer structure as shown below)

Property 2: Role configurable address and
each device can be connected to the bus by a unique address and other communication devices, the master / slave roles can be configured and address, the host can be used as the host transmitter and a host receiver.

Feature 3: multihost
IIC is a true multi-master bus, (IIC communication process may change the master), if two or more masters request the bus, the data bus can be prevented from being damaged by collision detection and arbitration.

Characteristics 4: transfer rate of
the transmission rate in standard mode can be achieved 100kb / s, the fast mode can be achieved 400kb / s.

5 Characteristics: load and the distance
the maximum number of nodes is limited address space and the bus capacitance. Also the total capacitance of the actual communication limit distance of a few meters.

3) protocol layer
a. Data Validation
Data Validation I2C protocol is ensured by the clock, within the high-level period of the clock, data on the SDA line must remain stable. Data line may be changed to a low level only when the clock SCL.

. B start and end conditions
starting conditions: when the SCL is high, SDA line from high to low transition is defined as the initial condition.
End Condition: when the SCL is high and the SDA line from low to high transition is defined as a STOP condition, attention should start and stop signals are issued by the host, the devices connected to the I2C bus, If the hardware interface with the I2C bus, it is easy to detect the start and termination signals.

Bus after the start condition, treated as busy, is considered idle after the stop condition.
c. response
whenever the host to the end of transmission of a byte from a slave, the master always necessary to wait for a response signal from a given machine, to determine whether the slave has received the data successfully, the host clock from answering machine is still required provided by the host, in response occurs immediately after the completion of every 8 data bits host transfer clock cycle, 0 represents a low level response, represents a non-responders
d. data in frame format
on the SDA line must be 8 byte per bit length, each of several bytes transmitted is not limited to transfer, behind each byte must be followed by an ACK. Firstly, using the most significant bit (MSB) transmitted.

2. IMX6ULL operation of the I2C controller and register Introduction

IMX6ULL的I2C提供了标准I2C从服务器和主服务器的功能，I2C是设计与标准的NXP I2C总线协议兼容，所以上面的通用知识完全可以应用在IMX6ULL I2C的编程和控制。
故我们只要熟悉IMX6ULL I2C重点寄存器即可。
（1）I2C Memory Map
I2C包含5个16-bit 的寄存器
注意：寄存器在偏移量0x0002/0x0006/0x000A/0x000E作为保留位。
可以看到I2C1的入口地址为21A_0000，这个我们重点关注，后面做实验，编程会使用到。

（2）Register
 I2C Address Register (I2Cx_IADR)

地址寄存器，偏移量为0h。
 bit15-8为保留位即只读为0。
 bit7-1（ADR）位是I2C作为从机时的地址。从属模式是I2C的默认模式，这个地址是作为从机的相应地址，不能被软件复位。
 I2C Frequency Divider Register (I2Cx_IFDR)

分频寄存器，偏移量为4h。
 bit15-6位为保留位即只读为0。
 bit5-1 位为I2C时钟频率
注意：该值在传输过程中不应该改变，但是可以在之前改变。
I2C_IFDR提供了一个可编程的预分频器，用于时钟配置以进行比特率选择，寄存器不会被软件重置。
寄存器IC位设置计算方法如下:

I2C的时钟源来源于IPG_CLK_ROOT=66Mhz
PLL2 = 528 MHz
PLL2_PFD2 = 528 MHz
IPG_CLK_ROOT = (PLL2_PFD2 / ahb_podf )/ ipg_podf = (528 MHz/4)/2 = 66Mhz
PER_CLK_ROOT = IPG_CLK_ROOT/perclk_podf = 66 MHz/1 = 66 MHz
设置I2C的波特率为100K， 因此当分频值=66000000/100000=660.
参考Table 31-3. I2C_IFDR Register Field Values 中只有640对应的0x15最接近

即寄存器IFDR的IC位设置为0X15

 I2C Control Register (I2Cx_I2CR)

控制寄存器，偏移量为8h
 bit 15-8为保留位即只读为0。
 bit 7 为I2C使能位。（0 disable，1 enable）
 bit 6 为I2C中断使能位。（0 disable，1 enable）
 bit 5 为主/从模式选择位（0 slave mode，1 master mode ）
 bit 4 为传输方向模式选择位 （0 receive mode，1 transmit mode）
 bit 3为应答使能位 （0 ACK , 1 NO ACK）
 bit 2 重复开始信号（0 no repeat start，1 Generates repeat start）
 bit 0 保留位

 I2C Status Register (I2Cx_I2SR)

状态寄存器，偏移量为Ch
 bit 15-8为保留位即只读为0。
 bit 7 数据传输状态位（0 传输中，1 传输完成）
 bit 6 I2C地址是否为从标识（0 不表示，1 是从机地址）
 bit 5 I2C总线忙状态标识位（0 空闲，1 忙 ）
 bit 4 仲裁丢失位 （0 正常，1 仲裁丢失）
 bit 3 保留位
 bit 2从机读写标识位 （0 slave接收，主向从写 , 1 slave发送 主向从读）
 bit 1 I2C中断（0无中断等待， 1有中断等待）
 bit 0 应答信号标识位（0检测到ACK， 1检测到NO ACK）

 I2C Data I/O Register (I2Cx_I2DR)

数据寄存器，偏移量为10h
 bit 15-8为保留位即只读为0。
 bit 7-1 数据字节
注意：在主接收模式下，读取数据寄存器允许发生读取并初始化下一个字节被接收。在从模式下，相同功能需要编址后生效。
低8位为有效数据位，发送数据时将数据写到这个寄存器中，如果要接收时直接读取该寄存器中的数据。

3. I2C控制器编程_框架

之前的所有铺垫都是为了实现I2C通讯，所以怎么用代码实现也是尤为关键的一个问题。
 初始化
因为不使用中断服务函数模式，初始化代码非常简单，我们仅需要将I2CR(bit7) 置0后写入IFDR为0x15，设置波特率为100k。（具体计算方法参考 2. IMX6ULL的I2C控制器操作与寄存器介绍中关于分频寄存器），然后再使能I2C，将I2CR(bit7)置1 。
01 I2C_BASE->I2CR &= ~(1 << 7);
02 I2C_BASE->IFDR = 0x15;
03 I2C_BASE->I2CR |= (1<<7);
 读写操作
下面是是I2C的读写标准流程，可能实际使用时根据需求略有异同。
写寄存器的标准流程如下图：

 1.Master发起START
 2.Master发送I2C addr（7bit）和w操作0（1bit），等待ACK
 3.Slave发送ACK
 4.Master发送reg addr（8bit），等待ACK
 5.Slave发送ACK
 6.Master发送data（8bit），即要写入寄存器中的数据，等待ACK
 7.Slave发送ACK
 8.第6步和第7步可以重复多次，即顺序写多个寄存器
 9.Master发起STOP

读寄存器的标准流程如下图：

 1.Master发送I2C addr（7bit）和w操作1（1bit），等待ACK
 2.Slave发送ACK
 3.Master发送reg addr（8bit），等待ACK
 4.Slave发送ACK
 5.Master发起RESTART
 6.Master发送I2C addr（7bit）和r操作1（1bit），等待ACK
 7.Slave发送ACK
 8.Slave发送data（8bit），即寄存器里的值
 9.Master发送ACK
 10.第8步和第9步可以重复多次，即顺序读多个寄存器
 11. Master发送NO ACK表示读取完成，从机也不用发送ACK
 12. Master发送STOP

4. I2C控制器编程_中断

I2C控制器中和中断有关的寄存器如下：
IIEN :I2C_I2CR（bit6）(0 disable I2C interrupt ，1 enable I2C interrupt)
IIF:I2C_I2SR (bit1) （0 No I2C interrupt pending ， 1 An interrupt is pending）
即中断使能位，中断状态位。
编码中在传送完1byte后可以通过判断IIF状态来确认ACK和传输完成。当然作为从机时，收到自己的地址后也可以进入中断。