system verilog (nine) functional coverage

Functional coverage: indicators used to measure a design feature which has been tested through the test program
first option is to use more seeds to run existing test procedures; followed by the establishment of new constraints, only when really needed it turn to directed tests
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(1) by varying the random seed, you can repeatedly run the same test platform to generate a new random excitation; each simulation will have a database with coverage information, this information can be combined functional coverage.
(2) If the coverage slowdown in growth, you need to add additional constraints to create more incentives; when a coverage ratio stabilized, and some Design has not yet been tested, then the need to create more new test,
(3) check the final approach 100% error rate in the functional coverage

1, code coverage : much more thorough test whether the test specifications for design implementation, not for verification plan; (how many lines of code has been executed (line coverage), there is a path through the code and expression in What has been executed (path coverage), the value of a single bit variable is 0 or 1 (flip cover), the state machine states and state transitions which have been accessed (finite state machine coverage)

2, functional coverage : design and intent are closely linked, and code coverage is a measure of the achievement of design. If this is a block of code in the design is missing, you can not find the error code coverage, functional coverage but you can.

3, the vulnerability of
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4, assertion coverage : assertion is a disposable or declarative code design relationship between two signals at a time kernel; simulation can follow along with the design and testbench, may also be in the form of inspection tool confirmed. (Asserted to find the most common errors, such as two signals are mutually exclusive or whether the request is permitted; once a problem is detected, the simulation will stop immediately assertion can also be used to check the arbitration algorithm, FIFO, and a variety of other hardware, such cases. use assert property statement)

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Functional coverage of a simple object

program automatic test(busifc.TB ifc);
class Transaction;
rand bit[31:0]data;
rand bit[2:0]port;
endclass

covergroup Covport;
coverpoint tr.port;
endgroup

initial
begin
Transaction tr;
CovPort ck;
ck=new();
tr=new();
repeat(32)begin
assert(tr.randomize);//创建一个事务
ifc.cb.port<=tr.port;
inc.cb.data<=tr.data;
ck.sample();
@ifc.cb;
end
endprogram

改进功能覆盖率最简单的方法是仅仅增加仿真时间或者尝试新的随机种子
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覆盖组(与类相似,一次定义后便可进行多次实例化)含有覆盖点、选项、形式参数和可选触发,一个覆盖组包含一个或多个数据点,在同一时间采集;可以定义在类中,也可以定义在程序或模块层次上,可以采样任何可见的变量;一个类中可以包含多个覆盖组,每个组根据需要自行使能或禁止。此外每个组可以有单独的触发,允许从多个源头收集数据。

在类中定义覆盖组:
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覆盖组的触发:功能覆盖率的两个主要部分是采样的数据和数据被采样的时刻,当这些数据都准备好之后,测试平台就会触发覆盖组(通过使用sample函数来完成,或者在covergroup的定义中使用阻塞表达式,阻塞表达式可以使用wait或@来实现在信号或事件上的阻塞。

event trans_ready;
covergroup CovPort@(trans_ready);
coverpoint ifc.cb.port;
endgroup

与直接调用sample方法相比,使用事件触发的好处在于能够借助已有的事件

使用sv断言进行触发:

module mem(simple_bus sb);
bit [7:0] data,addr;
event write_event;

cover property
(@(posedge sb.clock)sb.write_ena==1)
->write_event;
endmodule

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当你在覆盖点上指定一个变量或表达式时,sv便会创建很多“仓bin”来记录每个数值被捕获到的次数(这些仓是衡量功能覆盖率的基本单位),在每次仿真的末尾,所有带标记的仓会被汇集到一个新创建的数据库中。
为了计算一个点上的覆盖率,首先必须确定所有可能数值的个数,即域;覆盖率就是采样值的数目除以域中仓的数目。(sv会自动为覆盖点创建仓;其中覆盖组选项auto_bin_max指明了自动创建仓的最大数目,缺省值为64)
例如:使用auto_bin_max并将仓数设置成2

covergroup CovPort;
coverpoint tr.port
{options.auto_bin_max=2;}
endgroup

此时,八个port值被映射到两个bin里面。而且每个bin都有采样值
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对表达式进行采样(需要核对报告以确保能够得到预期的值)
例如:对一个3bit加4bit的加法表达式进行采样,只能得到16个仓,但是数据实际上可以达到0:23个字节,仓数可能不够;可以使用额外常量的表达式可以计算达到5bit精度
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自动生成的仓适用于匿名数值,如计数值、地址值或2的幂值,而对于其他数值,应该明确对仓命名,以增加准确度
例如:上例可改写成

covergroup CovLen;
len:coverpoint(tr.hdr_len+tr.payload_len+5'b0)
{bins len[]={[0:23]};
endgroup

只当覆盖点的仓名
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条件覆盖率:使用关键字iff给覆盖点添加条件(常用于在复位期间关闭覆盖以忽略掉一些杂散的触发)
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同样地,可以使用start和stop函数来控制覆盖组中独立的实例
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对于枚举类型,sv会为每个可能值创建一个仓

typedef enum {INIT,DECODE,IDLE}fsmstate_e;
fsmstate_e pstate,nstate;
covergroup cg_fsm;
coverpoint pstate;
endgroup

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翻转覆盖率:先确定覆盖点状态转移的次数(不但知道那些值出现过,而且知道这些值的变化过程)

covergroup CoverPort;
coverpoint port{
bins t1=(0=>1),(0=>2),(0=>3);
}
endgroup

使用范围表达式可以确定多个转换过程;表达式(1,2=>3,4)创建四个翻转过程
还可以确定任何长度的翻转次数,例如:(0=>1=>1=>1=>2);可以使用缩略形式
(0=>1[*3]=>2)

在状态和翻转中使用通配符:可以使用关键字wildcard创建多个状态或翻转,在表达式中,任何X、Z或?都会当成0或1的通配符
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除了使用明确定义仓来涵盖所有的期望值,也可以让sv自动创建仓,然后使用ignore_bins排除掉那些不用来计算功能覆盖率的值
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Illegal positions: some sample values not only should not occur, but if there should also be an error, you can use illegal_bins to warehouse identification.
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Cross Coverage: it can be measured simultaneously covering two or more points, if one kind of the N kinds of values, there are other kinds of M values, NXM cross bins need to store all the combinations.

class Transaction;
rand bit [3:0]kind;
rand bit[2:0] port;
endclass

Transaction tr;

covergroup CovPort;
kind:coverpoint tr.kind;
port:coverpoint tr.port;
cross kind,port;
endgroup

If you need to cross names more readable cartridge cover may also cover the respective positions of the individual reference points.
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Using the number ignore_bins can reduce the bin, in cross coverage may be used binsof and intersect specify coverage points and the set of values
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provided weights or no certain variables can be weight set to 0
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SV allows the creation of a universal coverage group, and it can be specified when instantiating some unique details can cover set into a class, then the trigger parameter passed to the constructor.
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Analysis of the coverage data
transaction length uneven distribution
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can solve ... before constraint
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can get_coverage () (with the group name and instance cover for covering a given group all instances of coverage) and get_inst_coverage () (return a specific covergroup examples of coverage)

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