SV - Verilog and System Verilog in literal representation

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0. Introduction

Literal (literal integer) is similar to the 5, 'h10 such values.

 

1. syntax

<size>'s<base><value>

• <size> is optional. If given, it specifies the total number of bits represented by the literal integer. If not given, the default size, per the Verilog/SystemVerilog standard is "at least"32 bits.
• s is optional. If given, it specifies thatthe literal integer should be treated as a signed value in operations. If not given, the default is unsigned. (The signed specifier wasadded to Verilog as part of the Verilog-200I standard.)
• <base> is required, and specifies whether the value is in binary, octal, decimal, or hex.
• <value> is required, andspecifies the literal integer value.

The baseoptions are represented using b, 0, d, or h for binary, octal, decimal andhex,
respectively. The base specifier can be either lowercase or uppercase (i.e. ' h 5
and ' H5 are the same).

2. Symbol

Unbased literal integers default to signed. Based literal integers default to unsigned.

For example 5, showing a signed 5; 'd5 represents unsigned 5.

3. reference

《Verilog and SystemVerilog Gotchas》