After countless written test interviews, I don’t know if you have discovered that digital IC’s written test interviews still have many commonalities and rules to follow. Therefore, you must master the frequently asked questions in the written test interview.
Summary of Frequently Asked Questions and Answers for Digital IC Written Exam Interviews
Verification direction (some topics)
Q1. The characteristics and usage of fixed-width arrays, dynamic arrays, associative arrays, and queues.
Queue: The queue combines the advantages of linked lists and arrays, and elements can be added or deleted at any position in a queue. It is declared by a symbol like []: intq[] It is declared by a symbol like: int q[] to declare:in tq [ ], widely used, multi-application and scoreboard;
Fixed-width array : It is a static array, and the size has been determined at compile time. It can be divided into compressed fixed-width arrays and uncompressed fixed-width arrays: compressed arrays are defined after the type and before the name; uncompressed arrays are defined after the name. Bit [7:0][3:0] name compressed array (storage space is continuous); bit[7:0] name [3:0] uncompressed array (storage space is not continuous);
Dynamic array: its memory space can only be determined at runtime, and new[] needs to be used to allocate space before use.
Associative array: It is mainly used when a large space is needed but not all data is needed. Similar to hash, it is composed of an index value and a data: bit [63:0] name[bit[63:0]]; index The value must be unique. The focus of this part is to learn the traversal method of the associative array.
Q2. Similarities and differences between fork...join/fork...join_any/fork...join_none
fork...join: The internal begin end block runs in parallel, and does not enter the next stage until all threads have finished running.
fork...join_any: The internal begin end blocks run in parallel, and any begin end block can enter the next stage after running.
fork...join_none: The internal begin end blocks run in parallel, and can go directly to the next stage without waiting.
Q3. The similarities and differences between mailbox, event, and semaphore.
Mailbox: It is mainly used for data communication between two threads, and the data is sent and obtained through the put function, get function and peek function.
event: The event is mainly used for a synchronous operation between two threads, and the operation synchronization between the two threads is performed through event triggering and event waiting. Use @(event) or wait(event.trigger) to wait, -> to trigger.
semaphore: The semaphore is mainly used for an interaction of resource access, and a thread can access a resource through key acquisition and return. Use the put and get functions to get the return key. Multiple at a time.
Q4. The difference between @(event_handle) and wait(event_handle.triggered)
@(event_handle): Edge trigger, the event will wait until it is triggered, blocking type;
wait(event_handle.triggered): level trigger, if the event is currently triggered, it will not cause blocking, non-blocking, when the event is triggered multiple times, avoid using wait.
Q5. The similarities and differences between task and function
function: there must be at least one input variable and one return value, which can only be used for pure numbers or logical operations;
task: Commonly used time-consuming statements can be built in, which may be used in time-consuming signal sampling or driving scenarios.
If you want to call a function, you can use both function and task to call it; if you want to call a task, it is recommended to use task to call, because if the called task has a built-in time-consuming statement, the method type that calls it externally must for task.
Q6. The benefits of using the clocking block
Interface: It is a set of interfaces used to encapsulate and bundle signals. If each signal is connected like in verilog, we need to define the interface signal at each layer. If there are too many signals, it is easy to cause human error, and the later reusability is not high. Therefore, using the interface interface to connect can not only simplify the code, but also improve reusability. In addition, the interface provides some other functions for synchronization between the test platform and the DUT and to avoid competition.
Clocking block: Inside the interface, we can define the clocking block, which can keep the signal synchronized. There are detailed setting operations for the sampling and driving of the interface, so as to avoid the interface competition between TB and DUT, and reduce our errors caused by signal competition. The sampling is advanced and the driving is behind to ensure that the signal will not compete.
Q7. The role and difference between synchronous FIFO and asynchronous FIFO
FIFO is a Simple Dual Port RAM whose address is incremented sequentially in hardware. It is divided into synchronous FIFO and asynchronous FIFO according to whether the clock domain of reading data and writing data is the same. Among them, synchronous FIFO FIFO means that the read clock and write clock are synchronous clocks, which are often used for data caching and data bit width conversion; asynchronous FIFO usually means that the read clock and write clock frequencies are different, that is, the FIFO driven by two asynchronous clocks, due to the read The write operation is independent, so it is often used for multi-bit data processing across clock domains.
Q8. Three major characteristics of OOP in SystemVerilog
Classes have three main characteristics: encapsulation, inheritance, and polymorphism.
Encapsulation: By encapsulating some data and methods of using these data in a collection, it becomes a class.
Inheritance: Allows to get a new class through an existing class, and it can share the properties and methods of the existing class. Existing classes are called base classes, and new classes are called derived or extended classes.
Polymorphism: After obtaining the extended class, sometimes we will use the base class handle to call the extended class object. How can the method called at this time accurately determine the method we want to call? By making a virtual declaration of the method in the class, when calling When the base class handle points to the extended class, the method will be identified according to the object, and the method of the extended class will be called instead of the method in the base class. The methods in the base class and the extended class have the same name, but can be called accurately, which is called polymorphism.
Q9. Detailed understanding of the ref type
The ref parameter type is a reference. When passing an array to a subroutine, try to use ref to obtain the best performance. If you do not want the subroutine to change the value of the array, you can use the const ref type. Variables can be modified in a task and the result of the modification is always visible to the function that calls it.
Q10. How to use external constraints and what are the ways
to use them:
class Packet; rand bit [7:0] length; rand bit [7:0] payload[];
constraint c_valid {length > 0;payload.size() == length;} constraint
c_external; endclass constraint Packet::c_external {length == 1;}
//外部约束
Randomization is an extremely important knowledge point in SV. By setting randomization and related constraints, we can automatically randomize the desired data.
Weight constraints dist: There are two operators: :=n :/n The first one means that each value has a weight of n, and the second means that each value has a weight of n/num.
Conditional constraints if else and -> (case): if else is the same as normal use; -> After the previous conditions are met, the following events can be triggered.
Range constraint inside: inside{[min:max]}; the range operator can also directly use the greater than less than symbol, and cannot be used continuously, such as min<wxm<max, which is wrong.
Front-end design direction (some topics)
1. What is synchronous logic and asynchronous logic?
Synchronous logic is a fixed causal relationship between clocks. Asynchronous logic is that there is no fixed causal relationship between clocks. The characteristics of the synchronous sequential logic circuit: the clock terminals of each flip-flop are all connected together and connected to the system clock terminal. Only when the clock pulse arrives, the state of the circuit can be changed.
The changed state will remain until the arrival of the next clock pulse. At this time, no matter whether the external input x changes or not, each state in the state table is stable. The characteristics of asynchronous sequential logic circuit: In addition to the flip-flop with clock, the flip-flop without clock and the delay element can also be used as the storage element in the circuit. There is no unified clock in the circuit, and the change of the circuit state is controlled by the external input changes directly.
2. The difference between synchronous circuit and asynchronous circuit:
synchronous circuit: the clock input terminals of all flip-flops in the storage circuit are connected to the same clock pulse source, so the state changes of all flip-flops are synchronized with the added clock pulse signal. Asynchronous circuit: The circuit does not have a unified clock. The clock input of some flip-flops is connected to the clock pulse source. Only the state changes of these flip-flops are synchronized with the clock pulse, while the state changes of other flip-flops are not synchronized with the clock pulse.
3. The essence of timing design:
the essence of timing design is to meet the setup/hold time requirements of each flip-flop.
4. What is the concept of establishing time and maintaining time?
Setup time: The minimum time that the data at the data input of a flip-flop must remain unchanged before the rising edge of the clock arrives. Hold time: The minimum time for which the data at the data input of a flip-flop must remain unchanged after the rising edge of the clock arrives.
5. Why does the flip-flop need to meet the setup time and hold time?
Because the formation of the internal data of the flip-flop takes a certain amount of time, if the setup and hold times are not met, the flip-flop will enter a metastable state, and the output of the flip-flop will be unstable after entering the metastable state, changing between 0 and 1 , it takes a recovery time for the output to stabilize, but the stabilized value is not necessarily your input value.
That's why two-stage flip-flops are used to synchronize asynchronous input signals. Doing so can prevent the metastable state generated by the flip-flop at this stage from propagating to the subsequent logic due to the fact that the asynchronous input signal may not satisfy the setup and hold time for the clock at this stage, resulting in the propagation of the metastable state. (easier to understand)
To understand it in another way: the establishment time is required because the D terminal of the flip-flop is receiving data like a latch. In order to stably set the state of the front-end gate, it takes a period of stabilization time; the hold time is required because after the clock edge arrives, the flip-flop To latch the state through feedback, it takes time to pass from the subsequent gate to the previous gate.
6. What is metastable state? Why does a two-stage flip-flop prevent metastable propagation?
This is also a question of synchronizing an asynchronous circuit. Metastability means that the flip-flop cannot reach an identifiable state within a specified period of time. A circuit that uses two-stage flip-flops to synchronize an asynchronous circuit is actually called a "one-bit synchronizer", and it can only be used to synchronize one-bit asynchronous signals.
The principle that the two-stage flip-flop can prevent metastable state propagation: Assuming that the input of the first-stage flip-flop does not meet its establishment and hold time, the data output by it after the arrival of the first pulse edge is metastable, then in the next pulse Before the edge arrives, the metastable data output by it must be stabilized after a period of recovery time, and the stable data must meet the establishment time of the second-stage flip-flop. If all are satisfied, when the next pulse edge arrives, the second-stage The flip-flop will not be metastable because the data at its input satisfies its setup and hold time. The condition for the synchronizer to be valid: the recovery time of the first-stage flip-flop after entering the metastable state + the setup time of the second-stage flip-flop <= clock period.
More precisely, the input pulse width must be greater than the sum of the synchronous clock period and the hold time required for the first-stage flip-flop. The safest pulse width is twice the synchronous clock period. Therefore, such a synchronous circuit is more effective for an asynchronous signal from a slower clock domain entering a faster clock domain, and is ineffective for entering a slower clock domain.
7. What are the concepts and basic strategies of timing constraints?
Timing constraints mainly include period constraints, offset constraints, and static timing path constraints. Through additional timing constraints, the synthesis and routing tools can adjust the mapping and placement and routing to make the design meet the timing requirements. The general strategy for attaching timing constraints is to attach global constraints first, and then attach specific constraints on the fast and slow exception paths.
When adding global constraints, first define all the clocks of the design, group the synchronous elements in each clock domain, add cycle constraints to the groups, and then add offset constraints to the FPGA/CPLD input and output PADs, and PAD TO PAD paths for full combinational logic Additional constraints. When attaching specialized constraints, first constrain the paths between groups, then constrain fast, slow exception paths and multi-cycle paths, and other special paths.
8. What is the difference between a latch and a flip-flop?
Level-sensitive memory devices are called latches. Can be divided into high-level latches and low-level latches for signal synchronization between different clocks. A bistable memory element composed of cross-coupled gates is called a flip-flop. It is divided into rising edge trigger and falling edge trigger. It can be considered that two different level-sensitive latches are connected in series. The former latch determines the setup time of the flip-flop, and the latter latch determines the hold time.
9. What two kinds of memory resources are there in the FPGA chip?
There are two kinds of memory resources in the FPGA chip: one is called BLOCK RAM, and the other is an internal memory configured by LUT (that is, distributed RAM). BLOCK RAM is composed of a certain number of fixed-size storage blocks. Using BLOCK RAM resources does not occupy additional logic resources and is fast. However, the BLOCK RAM resources consumed during use are integer multiples of the block size.
10. What is clock jitter?
Clock jitter refers to a temporary change in the clock cycle at a given point on the chip, which means that the clock cycle may be lengthened or shortened on different cycles. It is an average variable with a mean of 0.
Back-end direction (some topics)
• 1) Chip utilization depends on ___.
a.Only on standard cells
b.Standard cells and macros
c.Only on macros
d.Standard cells macros and IO pads
• 2) In Soft blockages ____ cells are placed.
a.Only sequential cells
b.No cells
c.Only Buffers and Inverters
d.Any cells
• 3) Why we have to remove scan chains before placement?
a.Because scan chains are group of flip flop
b.It does not have timing critical path
c.It is series of flip flop connected in FIFO
d.None
• 4) Delay between shortest path and longest path in the clock is called ____.
a.Useful skew
b.Local skew
c.Global skew
d.Slack
• 5) Cross talk can be avoided by ___.
a.Decreasing the spacing between the metal layers
b.Shielding the nets
c.Using lower metal layers
d.Using long nets
Please list which files are required to import the backend design?
This question is often used as a written test question to test students' ability to understand basic timing. In essence, the standard cell delay is determined by the input transition and output load of the cell. PVT is used as an external condition, and it will also affect the delay of the cell. It should be understood what is the relationship between PVT and delay? Suggestion: A more comprehensive answer is that under the same PVT conditions, cell delay is determined by input transition and output load
Please list a few sdc commands you know, and tell their purpose?
Review common sdc commands: describe the working speed of the chip, that is, the frequency of the clock, including create_clock, create_generated_clock, etc.
Describe the boundary constraints of the chip, including set_input_delay, set_output_delay, etc. Describe some design violations of the chip (DRV), including set_max_fanout, set_max_capacitance, set_max_transition, etc. Describe some special
paths in the design, including set_false_path, set_multicycle_path, etc.
Describe some timing arcs that need to be prohibited in the design, such as set_disable_timing
Please talk about the concept of drv, what are the main contents?
Why Max transition, max capacity, max fanout should be repaired first? It has been mentioned many times in the class. You need to remember that you can point out to the interviewer: max fanout does not need to be repaired.
Layout direction (some topics)
IC written test interview experience (26 major manufacturers)
Due to space limitations, I will not update all the topics one by one, and I can share the above with you. If you need written interview questions in that direction, you can get them on demand~
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