Written verification of digital IC and digital IC design often is done with a pen questions, so digital design experience compared to the students, the students do the verification of the written part is still a great disadvantage, but it is not irreparable. Pen questions focused on general basis, but the basic digital IC design related to the most commonly used methods and ideas related to the most common test are:
Across clock domains (1) signal synchronized. Including single bit and multi-bit, two-stage nature for single bit register synchronization most convenient. For a multi-bit, asynchronous FIFO often investigated and handshake method. To understand the concept and avoid metastable metastable method.
(2) When it comes to the metastable state, I have to say setup time and hold time. Be sure to master two clock constraints and methods for analyzing the clock constraints. Four ways for clear (input to output, the input to the register, register-to-register, register-to-output), and to find the critical path. It calculates the maximum operating frequency.
(3) analysis and repair setup time validation (reducing the clock frequency, resolution, or a combination of logic optimization, to improve the working voltage) and the hold time validation (insertion buffer, more difficult to repair)
(4) The circuit configuration can be commonly described verilog, such as: D flip-flop, a counter, frequency divider (divide an odd multiple, even multiples of frequency division, fractional frequency (e.g., 1.5)), the FIFO synchronous, asynchronous the FIFO, sequence detector (FSM implementation)
(5) verilog code with the description given in pseudo-code, or
(6) identify verilog code errors, such as clock signal is not cross-domain synchronization, no undesirable else branch will latch the like.
(7) blocking, non-blocking assignments
(8) sv base, including the difference between @signal trigger and wait (signal), the event trigger, queue operations, task synchronization schedule (usage differences fork ... join, fork ... join_any, fork ... join_none a) https: //zhuanlan.zhihu .com / p / 29642469https: //zhuanlan.zhihu.com/p/29642469
(9) have some common protocols, such as the I2C (capable of realizing the presentation verilog), SRAM Association, AMBA (AHB), AXI
(10) When using asynchronous reset What should be noted?
Asynchronous reset, synchronous release
(11) Plot the circuit configuration of the synchronous asynchronous reset release:
(12) in the verification environment, C how to access and register dut, is how to contact?
Verilog provides VPI interface hierarchy of the DUT can be open to external C / C ++ code, and systemverilog provides a better interface: DPI.
(13) have some common low-power method, such as clock gating (FIG circuit configuration can be shown), the DVFS understand, multi-threshold voltage technology, multi-voltage technology
(14) subject to a combination of the logic output register filtering glitches
Verify digital IC face questions:
Interview Preparation:
Fully prepared to introduce yourself before the interview, foreign companies can prepare for an English self-introduction, it is best to introduce their own project or task done in English. Then the most important thing is fully ready to resume what you wrote, write something on your resume that you must have a thorough understanding. If you have a project, then the best aspects of the project may be asked questions thought. Another easily overlooked is that many people choose to work on the grounds of the city is very well prepared, I eat a lot because of this loss. To be able to give very reasonable and persuasive reason to make the interviewer believe that you really want to go to that city to work and live, to show his sincerity. Otherwise it will make the interviewer wonder you're just reaping offer.
Technical: If you have project experience, then the interviewer is most concerned about is that you have not done a thorough grasp of their own projects. So be prepared before the interview it is very important, of course, this is based on your solid project experience. Of course, some interviewer if not interested in your project experience, he / she may ask you some basic knowledge. For example, I encountered the interviewer understand verify on the spot the one or two basic questions (such as COMS related, decimal counter circuit structure, only two-input NAND gate achieve two-input OR gate, etc.). Most of the time the final technical interviewer will ask you what the general problem, it is best to be prepared before the interview, prepare some related to career development, jobs and other issues. Usually in the technical side not to mention salary, because it is responsible for the HR section.
HR side: HR surface generally after the technical side through, this time we can detailed understanding of all aspects of the issue of compensation and benefits and other friends, including food, shelter, and other problems can ask questions.
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Briefly talk about the work you're doing now.
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Please talk about your project and learn in school.
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Please talk about your understanding of science UVM verification method.
UVM verification methodology is based on a highly efficient verification method systemverilog language form. Its main feature is to improve the reusability of code, so that staff can verify the code reuse transplant modify quickly build verification platform, which will focus on the preparation of specific test cases. On the other hand, UVM encapsulates a lot of useful methods, which makes verification does not have to focus so much on the underlying implementation, and reduce debugging time verification platform.
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Please talk about the relationship between UVM component.
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Examples of some common methods UVM components to talk.
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Please talk about the difference between virtual sequencer and sequencer, and why use virtual sequencer?
If only one drive end agent, apparently without the use of virtual sequencer.
If there are more drive agent, but there is no coordination between multiple excitation, virtual sequencer also unnecessary.
If more than one drive end agent, and there is coordination between multiple excitation, then the virtual sequencer is very necessary. This time the environment needs to include an even more virtual sequencer up.
What virtual sequence and virtual sequencer of "virtual" mean?
Virtual sequencer has three attributes:
(1) Virtual sequencer to control other sequencer
(2) Virtual sequencer and is not connected to any driver
(3) Virtual sequencer does not process the item
The sequencer is not as normal as the sequence item passed to the driver through the sequencer port. Virtual sequencer to specify a sequencer by pointing subsequencer goal handle. subsequencer here is the driver and sequencer with real connections. Refers to the so-called virtual real sequence is not generated and passed in the Virtual sequencer years. A virtual sequencer can produce a number of different types of tranction through its subsequencer. The role of virtual sequencer is in different coordinate subsequencer the sequence of execution of the order.
- Why sequence, sequencer, and a driver, and why would you apart? What are the benefits of this have to do?
The initial verification platform, the driver only needs to, why do we need sequence mechanism?
(1) if the transaction is defined in the driver inside, you will have a problem. For example, a wide range of affairs, is it every time you start a transaction, you must modify the code main_phase part of the driver.
(2) If the definition of a plurality of driver, then the tree structure UVM will engage mess. Therefore, peeling from the driver in generating a transaction (transaction definition specifically includes the step of generating the transaction) code portions. driver can drive only in charge of affairs.
(3) a supplement, verify case_list, is a mechanism to implement the sequence; and to ensure that the tree structure of the UVM unity, unity. Making ability maintainable greatly enhanced.
The above explanation, the reason is the sequence and sequence_item uvm_componet does not belong. case-related code changes are implemented in sequence and sequence_item years.
- Have you ever written assertion it? assertion which is divided into several? Quick description under the assertion of usage.
Systemverilog assertion belonging verification methods, assertions (assertions) is a description of the design attributes (property behavior), if a property is not what we expect, then the assertion will fail. assertions compared with verilog, verilog is a procedural language. It is designed to describe the hardware, it can be well controlled timing, but describe the complex timing relationships, the code is more verbose, assertions is a descriptive language, designed for the simulation, you can have a lot of built-in function to test specific timing relationships and automatically collect data coverage.
SVA is divided into immediate and concurrent assertion assertion two kinds. Concurrent assertion is based on a clock cycle, the calculation expression in the clock edge, which can be placed on the module (Module1), the interface (interface), or block (Program) definition, the keyword "property" is defined to be in static and dynamic verification tools used in verification tools. Instant assertion is based on change events, evaluate expressions like combinational logic assignment in verilog, it is to be evaluated immediately, regardless of the timing, the process must be placed in the block definition.
Concurrent assertions:
property a2b_p; // description attribute
@(posedge sclk) $rose(a) |->[2:4] $rose(b);
endproperty
a2b_a: assert property (a2b_p); // assert property SVA keywords represent concurrent assertion
a2b_c: cover property (a2b_p); // statement covering
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Describe the function module you have experience before.
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Fifo you familiar with it? Full of empty talk about how to determine the status of the fifo?
(1) Strict empty full judgment: w_ptrr_ptr loopback flag write phase and both empty, w_ptrr_ptr and write loop while flag is not full. This is usually no problem, but in general do asynchronous fifo pessimistic empty full judgment in sync fifo, the fifo in order to avoid empty read-write fifo won over.
(2) Conservative empty full judgment: and direction signs threshold. 75% FIFO capacity is set as the upper limit, 25% FIFO capacity is set as the lower limit. When the direction flag exceeds the threshold will output full / empty flag, in fact, when the output empty full flag FIFO is not necessarily really empty / full.
- There fifo and asynchronous synchronization, What's the difference?
Fifo read and write the same clock synchronization, asynchronous fifo read and write different clock.
- For asynchronous fifo, how to deal with synchronization issues when space is full? What method can also be used?
Read and write pointers into Gray code and then synchronize.
- Please talk about the idea of verification, validation differences and designers think of.
Verification will always be inadequate, it is not always the best, in the words of a colleague, if you have to set a deadline to verify it, I hope it is a thousand years.
Currently common practice is to look at coverage.
(1) Look design spec
(2) Learn the relevant agreement
(3) Write the test plan and verification spec
(4) build verification platform
(5). Testcases create test cases based on testplan
(6) simulation and debug, including environmental and design of the bug, the most time-consuming. Tools are VCS / verdi
debug tools are: View log, see waveform
(7). Regression and coverage
(8). code review
- What coverage you will consider the project?
Line coverage, condition coverage,branch coverage, toggle coverage, statement coverage（FSM）
- coverage generally do not directly reach 100%, when you have a condition found not to cover when you do that how?
Directional writing test cases (direct case)
16. Why should I avoid using absolute paths? How to avoid?
Using an absolute path greatly reduced portability verification platform. The method avoids the use of macros and interface.
- How to use the interface in the driver? why?
Since the driver is a class, the interface does not allow direct use in the class, it is used in the class virtual interface. Then top_tb by uvm_config_db # (virtual) :: set () ... way if set to the vif driver.
- You know callback mechanism UVM do?
The biggest use callback mechanism is to improve the verification platform reusability. It does this by using two different projects at the local callback function to do, and written in the same part of a complete env, when such reuse, as long as the change related to the callback function, env can achieve complete reuse.
In addition, callback is also used to build the test abnormalities, by overriding the factory mechanism can also achieve this.
18.OVM and UVM What is the difference?
UVM = + OVM, VMM (RAL)?
OVM register no solution, there are factory mechanism, however, after cadance launched RGM make up the short board, but using RGM require additional download, did not become part of the OVM. OVM has now stopped updating.
UVM almost entirely inherited OVM, at the same time adopted synopsysVMM the RAL register solutions, while absorbing some of the best implementations of the VMM. And mentor and candence2008年联合发布.
19.UVM between each component of how the organization operates, serial or parallel? If the serial, I ask by what mechanism to achieve operation between the components of scheduling?
Operational mechanisms for UVM, the UVM learned should be very clear, is that the relationship between the components, as well as Phase mechanism and so on. UVM is the essence of software, and the software are essentially running order, dut hardware is running in parallel. About operation scheduling between the components, only from the "UVM combat" this book is not the answer, and when I have a look at the SV Green Paper, the feeling to find the answer. Scheduling test platform is triggered by an event-driven (such as @,
->event）
20. A module for an encryption and decryption module to verify if the data to be encrypted is decrypted immediately, if it is found the same input data and output data, can be described both encryption and decryption module functions sister no problem? why?
This question is to see, at the time of reaction is should first be validated encryption module, respectively, if there is no problem, then verify together. But the interviewer on this issue seemingly not satisfied, ask why my direct experience not? I was all of a sudden could not say why.
21. When a module for the simulation of discovery: If you enter an address addr, found that the output is a dut same address addr, but the output of the reference model is addr1 Please analyze what might be the cause of the problem.? You will how to solve?
My first thought is that either dut design error, or reference model error. First we need to define spec check based on our reference model there is no problem, if there is no problem, debug the design through simulation, identify problems and find a designer repair. But the interviewer is still not satisfied, she concluded that I have not taken into account by the configuration register may work in different modes let dut, dut is not working in bypass mode, and the reference model work in other modes? At that time no thought of how you have to own it? A little ashamed, can reflect on afterwards and found her questioning itself is a problem, did not give enough information and guidance when to ask questions, not answer is reasonable. When down and interview the students also participated in the discussion of discovery, almost everyone was asked the same question.
forward from:
[1] https://zhuanlan.zhihu.com/p/29642469
