Table of contents
1 Introduction
At present, the basic ecology of udp implemented by fpga on the Internet is as follows:
1: udp transceiver written in verilog, but the FIFO or RAM in the middle calls IP, or does not have ping function, such code function can be used normally, but without ping function It’s basically waste, and you won’t use such code in actual projects. Just imagine, if there is a problem with multi-machine interconnection, your network card does not have a ping function, and you don’t even have a basic troubleshooting mechanism. Who would dare to use such a code? ?
2: The udp transceiver with ping function, the code is excellent and easy to use, but it is basically not open source, and the source code will not be provided to you. This kind of code also has shortcomings, that is, if there is a problem, I don’t know how to troubleshoot it. ;
3: Using Xilinx's Tri Mode Ethernet MAC triple-speed network IP implementation, this code is also very good, but still the same problem, there is no source code, and the triple-speed network IP needs a license, the triple-speed network IP has realized rgmii to gmii and then Conversion to axis;
4: Use FPGA’s GTX resource to use SFP optical port to realize UDP and communication. This solution can be completed without external network transformer;
5: UDP protocol stack implemented by verilog in the true sense Verilog implementation means that all codes of the UDP protocol stack use verilog codes, and are not applicable to any IP core, including FIFO, RAM, etc. Such a UDP protocol stack is very portable, and there are few such protocol stacks on the market, and it is almost difficult Get it, and it is such a protocol stack, huh, huh. . .
This design uses the UDP protocol stack implemented by pure verilog to realize the UDP loopback communication test. The output of the UDP protocol stack does not use the external network PHY, but calls Xilinx's 1G/2.5G Ethernet PCS/PMA or SGMII IP core to realize the function of the network PHY , the rate, the rate is fixed at 1G, the IP is configured as an SGMII output interface, and the UDP data sending and receiving function is realized through the SFP optical port; the user interface of the UDP protocol stack is AXIS, so that users do not need to care about the complicated UDP protocol but only need to care about the simple The user interface sequence can operate UDP sending and receiving, and the AXIS data interface can be simply looped back to complete the self-sending and self-receiving function, and use the network debugging assistant on the computer side to perform UDP sending and receiving verification;
This design is stable and reliable after a large number of repeated tests, and can be directly transplanted and used in the project. The engineering code can be comprehensively compiled and debugged on the board, and can be directly transplanted into the project. It is suitable for project development of students and graduate students, and also suitable for project development of on-the-job engineers. It can be applied to the digital communication field of medical, military and other industries;
provide complete and smooth engineering source code and technical support;
the method of obtaining engineering source code and technical support is at the end of the article, please be patient to the end;
2. The UDP scheme I have here
At present, I have a large number of project source codes of UDP protocol, including UDP data loopback, video transmission, AD acquisition and transmission, etc., as well as projects of TCP protocol. Brothers who need network communication can go and have a look: directly click to go
3. The performance of the UDP protocol stack
1: Pure verilog implementation, without using any IP core;
2: Portability ceiling, the protocol stack can be freely transplanted between Xilinx, Altera and other major FPGA models, because there is no IP, and the source language also has parameters to choose from ;
3: Strong adaptability, it has been successfully tested on RTL8211, B50610, and 88E1518 three phys, and the SFP interface of GT resources can also be used to realize UDP Ethernet communication; 4:
Timing convergence is in place;
5: Dynamic ARP function ;
6: Without ping function;
7: After RGMII is converted to GMII, it is output by the AXIS interface, which can completely replace Xilinx's Tri Mode Ethernet MAC IP core;
8: Supports a maximum rate of 1G;
4. Detailed design plan
The detailed design scheme is as follows:
SFP
This design does not need an external network PHY, but calls Xilinx's 1G/2.5G Ethernet PCS/PMA or SGMII IP core to realize the function of the network PHY, so the external interface is an SFP optical port, and the RX core TX of the SFP is connected to realize data loopback ;
GMII AXIS interface module
The code structure of the GMII AXIS interface module is as follows:
This module is used to connect to the GMII interface of the 1G/2.5G Ethernet PCS/PMA or SGMII IP core, and is the external interface of the UDP protocol stack, implemented with pure verilog code, including AXIS FIFO;
AXIS FIFO
Due to the use of AXIS data stream, AXIS FIFO must be used as the bridge of the elder brother module. The general design directly calls the AXIS FIFO IP core, but this design is implemented with pure verilog code for versatility and portability. The location of the code is as follows:
UDP protocol stack
The UDP protocol stack is implemented with pure verilog code, and the code structure is as follows:
the protocol stack is composed of ARP, IP layer, UDP layer, and AXIS FIFO modules, all of which are implemented with pure verilog code. The ARP layer implements the dynamic ARP function, and the IP layer and UDP layer Realize the data unpacking and grouping of the IP layer and UDP layer of the MAC data frame. This is the core operation of the UDP protocol. The state machine is very fake, so I won’t go into details here. The function of AXIS FIFO is to encapsulate the complex UDP protocol into AXIS data stream format as a user interface for developers to use. Developers don’t even need to understand it. The protocol inside, just use it as an AXIS FIFO;
1G/2.5G Ethernet PCS/PMA or SGMII
This design does not require an external network PHY, but calls Xilinx’s 1G/2.5G Ethernet PCS/PMA or SGMII IP core to implement the network PHY function. The IP configuration is as follows. In addition, the IP needs to be equipped with internal registers, which are as follows. The register configuration code is located in fpga.v file:
5. Detailed explanation of vivado project
Development board: Xilinx–>xc7k325tffg900-2;
development environment: Vivado2019.1;
MAC: 1G/2.5G Ethernet PCS/PMA or SGMII;
input\output: UDP network communication;
test item: data sending and receiving;
engineering code structure is as follows:
FPGA Resource consumption and power consumption estimates are as follows;
6. Board debugging verification and demonstration
Preparation
The development board is connected as follows, and then power on to download the bit:
First, set the IP address of the computer as follows:
The IP address of the development board is set in the code as follows, in fpga_core.v, you can modify it freely:
View ARP
Open cmd, enter arp -a to view the arp cache table of the computer, as follows:
UDP data loopback test
Open the network debugging assistant and configure it as follows:
The test results of sending data once are as follows:
The test results of sending data in a loop are as follows, and the time interval is 1 second:
7. Welfare: acquisition of engineering code
Benefits: Obtaining the engineering code
The code is too large to be sent by email, and it is sent by a certain degree network disk link. The
method of data acquisition: private, or the V business card at the end of the article.
The network disk information is as follows:
