FPGA pure verilog realizes CameraLink video receiving and sending, with engineering source code and technical support

1 Introduction

Currently, there are two schemes for FPGA to implement CameraLink video codec:
one is to use a dedicated codec chip, such as a typical DS90CR287; the other is to use FPGA to implement codec, and use FPGA serdes resources to achieve deserialization. FPGA resources and serdes resources are unnecessary. The disadvantage is that the operation is more difficult and requires a higher level of FPGA.

This article describes in detail the implementation design scheme of FPGA pure verilog to realize CameraLink video receiving and sending, the purpose is to verify the correctness of CameraLink decoding module and encoding module, the idea is this, because there is no CameraLink camera in the project, but the key must be verified CameraLink decoding module and encoding module, so we made such an ingenious design:
first collect the HDMI input video, decompose it into RGB data by the HDMI decoding module, and then send it to the CameraLink encoding module, the output is the LVDS differential video signal of CameraLink, and then put This signal is looped back to the CameraLink video input interface through the CameraLink video output interface, so that the FPGA receives the LVDS differential video signal of CameraLink, and then sends this signal to the CameraLink decoding module, which is decomposed into RGB video, and finally output to the display through the HDMI encoding module. ;In this way, the input and output are both HDMI video, but the CameraLink decoding module and encoding module are verified at the same time, but the output effect can be visually viewed through the monitor, which can be described as a very delicate solution, haha. . .

After the engineering code is compiled and passed, it can be debugged and verified on the board, and the project can be directly transplanted. It is suitable for students in school to do graduation design, graduate project development, and also for in-service engineers to do project development. It can be applied to digital imaging and images in medical, military and other industries. Transmission field;
provide complete and smooth project source code and technical support;
the method of obtaining project source code and technical support is at the end of the article, please be patient to read the end;

2. Basics of CameraLink protocol

Regarding this part, many bloggers on the Internet have explained it. I found a few articles to recommend brothers to learn theoretical knowledge: the
first link: click to go directly to
the second link, which is what I wrote before: click to go directly

3. Currently I have the CameraLink transceiver project

My CameraLink video column has many CaeraLink video codec solutions for FPGA, including CaeraLink receiving, CaeraLink sending, CaeraLink ordinary output display, and CaeraLink video splicing output, etc. The column link is as follows: Welcome to view: Click to go directly

4. Design plan

The detailed design scheme is as follows:

This scheme does not require a CameraLink camera, but your board needs to have a CameraLink camera interface or a separate adapter board with a CameraLink camera interface. The specific process is as follows: Video input: use a laptop to simulate video input
,
and Laptop resolution is set to 1280x720@60Hz;
HDMI decoding module:
input is TMDS differential video signal, that is, HDMI video signal, and outputs parallel RGB data, that is, standard VGA video timing; this video is used as the input of CameraLink encoding module;
CameraLink encoding module:
input is RGB video data, output is LVDS differential video signal of CameraLink, this signal is output through CameraLink video interface;
CameraLink video interface: standard SDR26 connector, a total of two, one as output, the other as output and input ;
CameraLink encoding module:
input is CameraLink LVDS differential video signal, output is parallel RGB data, that is, standard VGA video timing; this video is used as the input of HDMI encoding module; HDMI encoding module:
input
is RGB video, output is TMDS differential Video, output HDMI monitor display;

5. Detailed explanation of CameraLink decoding module

The design block diagram of the CameraLink decoding module is as follows:

The input signals of the CameraLink decoding module are as follows:
1 channel of differential clock, 4 channels of differential data; use Xilinx official IDELAY and ISERDES source language to realize serial-to-parallel conversion;
IDELAY source language is used for delay, so that FPGA The CameraLink video data during sampling is stable;
the function of the ISERDES source language is to realize the serial-to-parallel conversion of CameraLink video data;
the entire CameraLink decoding module is implemented strictly according to the design block diagram, mainly calling the source language, so there is nothing to talk about, see for details Code, the amount of code is very small;
the parameters of the CameraLink decoding module are configured as follows:

these two parameters can be freely configured to adapt to different modes of CameraLink cameras; the specific configuration is as follows:

the currently configured mode is suitable for Base mode;

6. Detailed Explanation of CameraLink Encoding Module

The design block diagram of the CameraLink encoding module is as follows:

The CameraLink encoding module is the inverse process of decoding, and the input signals are as follows:
1-way single-ended clock, parallel pixel data; use Xilinx official OSERDES source language to realize parallel-to-serial conversion;
as encoding, no IDELAY source is required language delay;
the function of the OSERDES source language is to realize the parallel-to-serial conversion of CameraLink video data;
the entire CameraLink encoding module is implemented strictly according to the design block diagram, mainly calling the source language, so there is nothing to talk about, look at the code specifically, the amount of code is very large Less;
CameraLink encoding module parameter configuration is as follows:

These two parameters can be freely configured to adapt to different modes of CameraLink cameras; the specific configuration is as follows: the

current configured mode is suitable for Base mode;

7. Detailed explanation of vivado project

Development board FPGA model: xc7k325tffg676-2;
development environment: vivado2019.1;
input: HDMI, as the input of the CameraLink encoding module;
output: HDMI, essentially the output of the CameraLink decoding module;

The design of Bolck Design is as follows:

the integrated project code structure is as follows:

the estimated FPGA resource consumption and power consumption after comprehensive compilation are as follows:

8. Board debugging and verification

Since the CamerLink adapter board is inconvenient to leave the country, only the FPGA board and the corresponding CamerLink adapter board interface are displayed, as follows: the

output effect is as follows:

9. Welfare: acquisition of engineering code

Benefits: Obtaining the engineering code
The code is too large to be sent by email, and it is sent by a link to a certain network disk.
Data acquisition method 1: private, or the V business card at the end of the article.
The network disk information is as follows: