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1 Introduction
H264 video compression and decoding are widely used in the field of FPGA image transmission. Xilinx high-end devices have embedded H264 accelerators, which can be used by calling the API under the Linux system. However, for H264 video compression and decoding applications or learning that require custom private algorithms or protocols For researchers, pure verilog code to achieve H264 video compression is still of practical value. This design uses pure verilog code to realize H264 video compression without using any IP, which has reference value;
This article describes in detail the design scheme of FPGA pure verilog code to realize H264 video compression. The engineering code can be comprehensively compiled and debugged on the board, but at present it only achieves the simulation level, and can be directly transplanted to the project. For in-service engineers to do project development, it can be applied to the fields of digital imaging and image compression in medical, military and other industries;
provide complete and smooth engineering source code and technical support;
the method of obtaining engineering source code and technical support is at the end of the article, Please be patient until the end;
2. The video image codec scheme I have here
I have image JPEG decompression, JPEG-LS compression, H264 codec, H265 codec and other solutions, and there will be more solutions in the future. I will integrate them into a column and will continue to update. Column address:
direct click to go
3. H264 video compression theory
Please refer to this article, it feels very well written: https://blog.csdn.net/Ciellee/article/details/91375879
4. H264 video compression - performance
AVC/H.264 Baseline Profile
YUV 4:2:0 video source input;
video color depth 8bit;
maximum support 1080P@60Hz video;
GOP: I/P means intra/inter frame algorithm
MB: 16x16 means internal 16x16 image block
1/4 Sub-pixel interpolation
Search range: 16
All Inter Partition mode
All 9 Intra prediction mode
CAVLC
Deblocking Filter
INTRA – Intra mode decision & partition decision
a.Modify the mode priority of C model to match RTL
IME – Integer motion estimation
a.Modify the generation of mv_cost to support P frame
FME– Fractional motion estimation
a.Fix some bugs in fmv calculation and luma prediction
b.Redesign the 1/2 interpolator logic
TQ - Transformation & Quantization
a.Add QPc to quantize chroma residuals
b.Incease the bitwidth of quant modules and idct module to prevent overflow
CAVLC - Entropy coding
a.Modify the FSM to encode chroma component properly
b.Fix a bug in fetching residuals from TQ
FETCH
a.Fix several bugs in fetching predicted pixels
b.Modify the logic of reading RAM
5. H264 video compression - design scheme
The design block diagram is as follows:
Input: YUV 4:2:0 video stream; color depth 8bit; maximum support 1080P@60Hz video;
compression algorithm: inter-frame and intra-frame adaptive pipeline design; where I frame is stored in the module internal Buffer, P frame Output the external Buffer of the module; refer to the theoretical link in Section 3 for the detailed design algorithm; https://blog.csdn.net/Ciellee/article/details/91375879
output: single-byte H264 compressed data;
the top-level interface of the H264 video compression code is as follows :
module helai_h264_encode_2023 (
input clk ,
input rst_n ,
input i_sys_start , //开始压缩信号,高电平脉冲
output o_sys_done , //压缩完成指示信号,高有效
input i_sys_intra_flag, //开始GOP信号,高电平脉冲
input [5:0] i_sys_qp , //初始化QP值
input i_sys_mode , //0:frame mode 1:MB mode
input [`PIC_W_MB_LEN-1:0] i_sys_x_total , //一行图像的 MB 大小
input [`PIC_H_MB_LEN-1:0] i_sys_y_total , //一列图像的 MB 大小
output o_enc_ld_start ,
output [`PIC_W_MB_LEN-1:0] o_enc_ld_x ,
output [`PIC_H_MB_LEN-1:0] o_enc_ld_y ,
input [8*`BIT_DEPTH - 1:0] i_video_data , //视频数据输入
input i_video_de , //视频输入有效信号,高有效
output o_video_in_ing , //表示图像正在输入
output [7:0] o_video_data , //压缩后的视频数据输出
output o_video_de , //压缩后的视频数据输出有效信号,高有效
output [`PIC_W_MB_LEN-1:0] o_ext_PF_mb_x , //输出 P 帧一行图像的 MB 大小
output [`PIC_H_MB_LEN-1:0] o_ext_PF_mb_y , //输出 P 帧一列图像的 MB 大小
output o_ext_PF_start , //输出 P 帧开始信号,高电平,相当于 VGA 时序的 VS
input i_ext_PF_done , //输入 P 帧 Buffer 接收完成信号
output [2:0] o_ext_PF_mode , //输出 P 帧模式:0:frame mode 1:MB mode
input i_ext_PF_wen , //外部 P 帧 Buffer 输入写信号, 高有效
input i_ext_PF_ren , //外部 P 帧 Buffer 输入读信号, 高有效
input [3:0] i_ext_PF_addr , //外部 P 帧 Buffer 输入地址
input [16*`BIT_DEPTH - 1:0] i_ext_PF_data , //读回 P 帧 Buffer 的视频
output [4*4*`BIT_DEPTH - 1:0] o_ext_PF_data //写入 P 帧 Buffer 的视频
);
6. Detailed explanation of Vivado project
Create a Vivado project and copy the source code in for functional simulation and synthesis;
development board FPGA model: xc7k325tffg676-2;
input: test stimulus YUV 4:2:0 video stream file;
output: compressed video generated by software and compressed by FPGA Video comparison results byte by byte;
application: functional simulation and synthesis;
The code structure is as follows:
the FPGA resource consumption after synthesis is as follows:
7. Vivado function simulation
Due to the complexity of the simulation process, I specially made a PPT tutorial, which describes the simulation process in detail, hand-in-hand tutorials, and PPT tutorials are given in the data package; the location is as follows: the correct
simulation results are as follows:
8. Benefits: Acquisition of engineering codes
Benefits: Obtaining the engineering code
The code is too large to be sent by email. It will be sent via a certain network disk link, and
the data acquisition method: the V business card at the end of the article.
The network disk information is as follows:
