FPGA high-end project: 4K HDMI video transceiver routine based on GTH, providing engineering source code and technical support

FPGA high-end project: 4K HDMI video transceiver routine based on GTH, providing engineering source code and technical support

1 Introduction

Even those who have never played with GT high-speed interface and 4K high-definition video are embarrassed to say that they have played with FPGA. This is what a CSDN boss said, and I firmly believe it. . . GT resources are an important selling point of Xilinx series FPGAs and are also the basis for high-speed interfaces. Whether it is PCIE, SATA, MAC, etc., GT resources are needed for high-speed data serialization and deserialization. Different Xilinx FPGA series have different GT resource types, the low-end A7 has GTP, the K7 has GTX, the V7 has GTH, and the higher-end U+ series has GTY, etc. Their speeds are getting higher and higher, and their application scenarios are becoming more and more high-end. . . 4K high-definition video requires a large rate and bandwidth, and traditional IO can no longer meet it. It can only be achieved by using the GT high-speed interface of FPGA;

This article uses the GTH high-speed interface resource of the xczu7ev-ffvc1156-2-i model FPGA of Xilinx's Zynq UltraScale+MPSoCs series to conduct a 4K @60Hz HDMI video transceiver experiment. The 4K @60Hz video source first enters the onboard TMDS181IRGZT chip for leveling Convert, and then connect the differential video signal directly to the GTH high-speed transceiver BANK223; call the Xilinx official Video PHY Controller IP core to receive the 4K high-definition video and perform deserialization work, decoding the original high-speed serial signal into 3-channel 20-bit AXI4-Stream For parallel data, the IP uses FPGA GT resources, that is, GTH; then calls Xilinx's official HDMI 1.4/2.0 Receiver Subsystem IP core to decode 4K high-definition video. The IP simultaneously decodes the audio stream core video stream and streams it with AXI4-Stream Output; then Xilinx official Video Test Pattem Generator (TPG), the decoded AXI4-Stream video stream enters TPG, the IP outputs color bar video when no external AXI4-Stream video stream enters, otherwise it outputs external AXI4-Stream video; At the same time, add the audio generation module (aud_pat_gen.v) and audio acr control module (hdmi_acr_ctrl.v) officially recommended by Xilinx. The decoded AXI4-Stream audio stream enters these two modules for processing; at this point, the HDMI decoding work has been completed. At this point, the decoded video can be personalized, such as caching, scaling, convolution, etc. This project only performs loopback output operations; then Xilinx's official HDMI 1.4/2.0 Transmitter Subsystem IP core performs 4K high-definition video encoding. Work, encoding video streams and audio streams at the same time, outputting 3 AXI4-Stream streams and DDC control signals; 3 AXI4-Stream streams enter the Video PHY Controller IP core called earlier to perform 4K high-definition video and serialize the original 3 The 20-bit AXI4-Stream parallel data is serialized into a high-speed serial signal. This IP uses FPGA GT resources, that is, GTH; the output differential video signal is output from the GTH high-speed transceiver BANK223 and enters the onboard SN65DP159RGZ chip for power generation. flat conversion, and then connected to the HDMI output interface; many onboard chips require i2c configuration, and many IP cores called also need to be configured, so the Zynq soft core needs to be called for configuration. The Zynq soft core development tool is Vitis SDK, using ARM Run the C language software code and configure the IP register through the AXI-Lite bus. Two projects were made in the Vitis SDK software project. Project 1 is 4K HDMI video loopback, that is, receive-send; Project 2 is 4K HDMI video transmission. , that is, sending color bar video to the outside; connect a 4K monitor, download the bit and you can see the output 4K HDMI video;

Notice!
Notice!
Notice!
The FPGA used in this project is a high-end device, and the resources used are also high-end resources. It requires extremely high proficiency requirements for FPGA GT high-speed interface, image processing, FPGA heterogeneous characteristics, C language embedded programming, etc., so this project The source code is not suitable for novices or novices, but is only suitable for engineers or graduate students with work experience; novices or novices please block it yourself;

This blog describes in detail the design of the GTH high-speed interface resource of the xczu7ev-ffvc1156-2-i model FPGA of the Zynq UltraScale+MPSoCs series for 4K @60Hz HDMI video transceiver experiments. The engineering code can be comprehensively compiled and debugged on the board, and can be directly used in the project Transplantation is suitable for school students and graduate project development, and is also suitable for on-the-job engineers to learn and improve. It can be applied to high-speed interfaces or image processing fields in medical, military and other industries; it
provides complete and run-through engineering source code and technical support;
How to obtain the project source code and technical support is at the end of the article, please be patient and read to the end;

Disclaimer

This project and its source code include both parts written by myself and parts obtained from public channels on the Internet (including CSDN, Xilinx official website, Altera official website, etc.). If you feel offended, please send a private message to criticize and educate; based on this, this project The project and its source code are limited to readers or fans for personal study and research, and are prohibited from being used for commercial purposes. If legal issues arise due to commercial use by readers or fans themselves, this blog and the blogger have nothing to do with it, so please use it with caution. . .

2. Recommendation of relevant solutions

My existing GT high-speed interface solution

My homepage has a FPGA GT high-speed interface column. This column has video transmission routines and PCIE transmission routines for GT resources such as GTP, GTX, GTH, GTY, etc. GTP is based on the A7 series FPGA development board, and GTX is based on the K7 or ZYNQ series. FPGA development board is built, GTH is built based on KU or V7 series FPGA development board, GTY is built based on KU+ series FPGA development board; the following is the column address:
click to go directly

My existing FPGA image processing solution

My homepage currently has an FPGA image processing column. The new column includes the FPGA image processing solutions I currently have, including image scaling, image recognition, image splicing, image fusion, image defogging, image overlay, image rotation, image Enhancement, image character overlay, etc.; the following is the column address:
click to go directly

3. Detailed design plan

This article uses the GTH high-speed interface resource of the xczu7ev-ffvc1156-2-i model FPGA of Xilinx's Zynq UltraScale+MPSoCs series to conduct a 4K @60Hz HDMI video transceiver experiment. The 4K @60Hz video source first enters the onboard TMDS181IRGZT chip for leveling Convert, and then connect the differential video signal directly to the GTH high-speed transceiver BANK223; call the Xilinx official Video PHY Controller IP core to receive the 4K high-definition video and perform deserialization work, decoding the original high-speed serial signal into 3-channel 20-bit AXI4-Stream For parallel data, the IP uses FPGA GT resources, that is, GTH; then calls Xilinx's official HDMI 1.4/2.0 Receiver Subsystem IP core to decode 4K high-definition video. The IP simultaneously decodes the audio stream core video stream and streams it with AXI4-Stream Output; then Xilinx official Video Test Pattem Generator (TPG), the decoded AXI4-Stream video stream enters TPG, the IP outputs color bar video when no external AXI4-Stream video stream enters, otherwise it outputs external AXI4-Stream video; At the same time, add the audio generation module (aud_pat_gen.v) and audio acr control module (hdmi_acr_ctrl.v) officially recommended by Xilinx. The decoded AXI4-Stream audio stream enters these two modules for processing; at this point, the HDMI decoding work has been completed. At this point, the decoded video can be personalized, such as caching, scaling, convolution, etc. This project only performs loopback output operations; then Xilinx's official HDMI 1.4/2.0 Transmitter Subsystem IP core performs 4K high-definition video encoding. Work, encoding video streams and audio streams at the same time, outputting 3 AXI4-Stream streams and DDC control signals; 3 AXI4-Stream streams enter the Video PHY Controller IP core called earlier to perform 4K high-definition video and serialize the original 3 The 20-bit AXI4-Stream parallel data is serialized into a high-speed serial signal. This IP uses FPGA GT resources, that is, GTH; the output differential video signal is output from the GTH high-speed transceiver BANK223 and enters the onboard SN65DP159RGZ chip for power generation. flat conversion, and then connected to the HDMI output interface; many onboard chips require i2c configuration, and many IP cores called also need to be configured, so the Zynq soft core needs to be called for configuration. The Zynq soft core development tool is Vitis SDK, using ARM Run the C language software code and configure the IP register through the AXI-Lite bus. Two projects were made in the Vitis SDK software project. Project 1 is 4K HDMI video loopback, that is, receive-send; Project 2 is 4K HDMI video transmission. , that is, sending color bar video to the outside; connect a 4K monitor, download the bit and you can see the output 4K HDMI video;

Design block diagram

This design uses the solution officially recommended by Xilinx, which is roughly as follows:

The detailed design plan block diagram of the project specific to this design is as follows:

4K HDMI input hardware solution

The solution recommended by Xilinx is used here, that is, the TMDS181IRGZT chip is used for level conversion, and then the differential video signal is directly connected to the GTH high-speed transceiver BANK223. Other solutions are certainly possible, but there are not many companies currently developing this area, so for the sake of stability Considering it, it is better to use the solution recommended by Xilinx. The main schematic diagram is as follows:

Video PHY Controller

This IP must be used for 4K HDMI video transceiver using XIlinx solution. Video PHY Controller IP core mainly does deserialization and serialization work, using FPGA GT resources, that is, using GTH; at the receiving end, 4K high-definition video is received and deserialized Work, decode the original high-speed serial signal into three channels of 20-bit AXI4-Stream parallel data, make 4K high-definition video at the sending end and perform serialization work, and serialize the original three-channel 20-bit AXI4-Stream parallel data into high-speed serial Signal; Video PHY Controller configuration is as follows:

This IP requires further detailed configuration in Vitis SDK. For details, refer to the Vitis SDK C language software code;

HDMI 1.4/2.0 Receiver Subsystem

This IP must be used when using the XIlinx solution to do 4K HDMI video transceiver. The 4K HDMI input video is deserialized by the Video PHY Controller and then input into the HDMI 1.4/2.0 Receiver Subsystem IP. This IP does the decoding of 4K high-definition video, and the IP decodes the audio at the same time. Stream core video stream is output as AXI4-Stream stream; HDMI 1.4/2.0 Receiver Subsystemr configuration is as follows:

This IP requires further detailed configuration in Vitis SDK. For details, refer to Vitis SDK C language software code;

The trend of video streaming after 4K HDMI decoding

The HDMI 1.4/2.0 Receiver Subsystem simultaneously decodes the video stream and audio stream in the AXI4-Stream format. The video stream is input to the Xilinx official Video Test Pattem Generator IP core (TPG). The IP outputs color when no external AXI4-Stream video stream enters. video, otherwise the external AXI4-Stream video will be output; TPG is used with AXI-GPIO reset, and the IP group is encapsulated, as follows:

After expansion, the TPG configuration is as follows:


The IP needs further detailed configuration in the Vitis SDK, please refer to the Vitis SDK for details C language software code;

The trend of audio streaming after 4K HDMI decoding

HDMI 1.4/2.0 Receiver Subsystem simultaneously decodes the video stream and audio stream in AXI4-Stream format. The audio stream is input to Xilinx’s official audio generation module (aud_pat_gen.v) and audio acr control module (hdmi_acr_ctrl.v). The decoded AXI4- The Stream audio stream enters these two modules for processing; the two modules are encapsulated as follows:

expanded as follows:

These two modules require further detailed configuration in the Vitis SDK. For details, refer to the Vitis SDK C language software code;

HDMI 1.4/2.0 Transmitter Subsystem

This IP must be used to do 4K HDMI video transceiver using the XIlinx solution. The 4K HDMI video that needs to be output first enters the Xilinx official HDMI 1.4/2.0 Transmitter Subsystem IP core to do the encoding of 4K high-definition video, and encodes the video stream and audio stream at the same time. Output 3 channels of AXI4-Stream streams and DDC control signals; the 3 channels of AXI4-Stream streams enter the Video PHY Controller IP core called earlier to perform 4K high-definition video and serialization work, and serialize the original 3 channels of 20-bit AXI4-Stream parallel data. It is a high-speed serial signal; the DMI 1.4/2.0 Transmitter Subsystem configuration is as follows:

This IP requires further detailed configuration in the Vitis SDK. For details, refer to the Vitis SDK C language software code;

4K HDMI output hardware solution

The solution recommended by Xilinx is used here, that is, the SN65DP159RGZ chip does level conversion. The output differential video signal is output from the GTH high-speed transceiver BANK223, enters the onboard SN65DP159RGZ chip for level conversion, and then connects to the HDMI output interface; other solutions It is certainly possible, but there are not many companies currently developing this area, so for the sake of stability, it is better to use the solution recommended by Xilinx. The main schematics are as follows:

4. Detailed explanation of vivado project

PL side FPGA logic design engineering

Development board FPGA model: Xilinx–Zynq UltraScale+MPSoCs–xczu7ev-ffvc1156-2-i;
Development environment: Vivado2022.2;
Input: HDMI, resolution 4K @60Hz;
Output: HDMI, resolution 4K @60Hz;
Engineering functions: FPGA high-end project: 4K HDMI video transceiver based on GTH;
the project BD is as follows:

the project code structure is as follows:

the resource consumption and power consumption of the project are as follows:

PS terminal Vitis SDK software design project

The Vitis SDK software on the PS side still refers to the design solution officially recommended by Xilinx. It mainly configures a series of hardware chips and IP. Two projects are done in the Vitis SDK software project. Project 1 is 4K HDMI video loopback, that is, Receive – send; Project 2 is 4K HDMI video sending, that is, sending color bar video to the outside world; the project code structure is as follows: The

source code is expanded as follows:

Since it refers to the design scheme officially recommended by Xilinx, the code is very lengthy, and many codes are not needed Yes, there is a BUG in the official code, which caused the compilation to fail. I have fixed the BUG, ​​but still retain the verbosity of the code. Although it does not look good, the functionality is not affected;

5. Project transplantation instructions

Vivado version inconsistency handling

1: If your vivado version is consistent with the vivado version of this project, open the project directly;
2: If your vivado version is lower than the vivado version of this project, you need to open the project and click File –> Save As; but this method does not It is not safe. The safest way is to upgrade your vivado version to the vivado version of this project or a higher version;

3: If your vivado version is higher than the vivado version of this project, the solution is as follows:

After opening the project, you will find that the IP has been It is locked, as follows:

At this time, the IP needs to be upgraded, and the operation is as follows:

FPGA model inconsistency handling

If your FPGA model is inconsistent with mine, you need to change the FPGA model. The operation is as follows:



After changing the FPGA model, you also need to upgrade the IP. The method of upgrading the IP has been described previously;

Other considerations

1: Since the DDR of each board is not necessarily exactly the same, the MIG IP needs to be configured according to your own schematic. You can even directly delete the MIG of my original project and re-add the IP and reconfigure it;
2: According to your own To modify the pin constraints of the schematic diagram, just modify it in the xdc file;
3: When transplanting pure FPGA to Zynq, you need to add the zynq soft core to the project;

6. Board debugging, verification and demonstration

Preparation

FPGA development board, I use Zynq UltraScale+MPSoCs xczu7ev;
4K HDMI input source;
4K HDMI display;
4K HDMI cable;
download the bit after connecting the device;

Output static presentation

The output static demonstration is as follows:

It can be seen that the clarity and color brightness of 4K video are very beautiful and cannot be compared with low-end cameras;

Output dynamic demonstration

A short video was recorded, and the output dynamic demonstration is as follows:

4K HDMI

7. Benefits: Obtain project source code

Bonus: Acquisition of engineering code.
The code is too large and cannot be sent by email. It will be sent via a certain network disk link.
The information acquisition method is: private, or the V business card at the end of the article.
The network disk information is as follows: