Table of contents
1 Introduction
PCIE (PCI Express) adopts the current popular point-to-point serial connection in the industry. Compared with the shared parallel architecture of PCI and earlier computer buses, each device has its own dedicated connection. It does not need to request bandwidth from the entire bus, and it can Improving the data transmission rate to a very high frequency and achieving the high bandwidth that PCI cannot provide is the preferred direction of high-speed interfaces in various industries at present, and has high practical value and learning value;
This design uses Xilinx's official XDMA solution to build a PCIE communication platform based on Xilinx series FPGAs. This solution is only applicable to Xilinx series FPGAs. It also provides XDMA installation drivers and QT host computer source codes, eliminating the need to use XDMA tedious drivers. I am at a loss for finding and developing PC software, and building a vivado project, saves the embarrassment of not knowing how to use XDMA, making the use of PCIE easy to use, without having to care about its complicated PCIE protocol; because I The development board only supports PCIE X4, so the code provided is PCIE X4 architecture. If you need friends with PCIE X1, X2, X8, X16, X32, you can modify this project by yourself, or follow me, I will release new projects in real time .
This project realizes the basic PCIE communication, and conducts a speed test with the QT host computer.
This article describes in detail the design scheme of building a PCIE communication platform based on XDMA. The engineering code can be comprehensively compiled and debugged on the board, and can be directly transplanted. High-speed interface fields in medical, military and other industries;
provide complete and smooth engineering source code and technical support;
the method of obtaining engineering source code and technical support is at the end of the article, please be patient to the end;
2. My existing PCIE solution
My homepage has a PCIE communication column, including PCIE solutions based on RIFFA and PCIE solutions based on XDMA; there are simple data interaction, speed measurement, and application-level image acquisition and transmission. The following is the address of the column: Click to go
directly
3. PCIE theory
For this part, you can learn theoretical knowledge from Baidu or csdn or Zhihu. In fact, XDMA is used, and there is no need for complex protocols and theories until PCIE. . .
4. Overall design idea and plan
The overall design idea and scheme are as follows:
The PCIe communication routine consists of three parts: FPGA-side program, PCIe card driver, and PCIe host computer test program:
FPGA-side project: responsible for establishing the FPGA framework required for communication with PCIe, and the construction of the PCIe communication protocol ;
PCIe driver: responsible for the data exchange between the host computer test program and the PCIe card;
PCIe host computer test program: here is PCIe speed measurement;
The PICe clock input is connected to an external PCIe clock 100M (such as the PCIe slot of the chassis) through the PCIe interface to provide a reference clock for the operation of the PCIe communication module; the ddr clock input module provides a reference clock for the DDR controller; when the PCIe performs a write speed test, the upper The computer continuously sends test data to the PCIe communication module, and then transmits the data to the DDR controller, and the DDR controller will store the data in the DDR3 chip by itself; when the PCIe performs a read speed test, the DDR controller will obtain the data in the DDR3 chip, Then transmit the data to the PCIe communication module, and the host computer continuously obtains the test data from the PCIe communication module; when the PCIe performs the read and write speed test, it controls the PCIe write speed test while performing the PCIe read speed test. The process is a combination of the above-mentioned write speed and read speed tests.
QT speed measurement host computer: provide source code and executable program, and the developed version is QT5.6.2;
PCIE driver: provide Win system driver;
XDMA: call the official IP, configure it in X4 mode;
AXI MIG: call the official IP, as a data cache ;
5. Detailed explanation of vivado project
Development board FPGA model: Xilinx xc7a100tfgg484-2;
development environment: Vivado2019.1;
input/output: PCIE X4;
application: QT host computer speed test;
project BD is as follows:
the integrated project code structure is as follows:
FPGA after comprehensive compilation Resource consumption and power consumption estimates are as follows:
6. Driver installation
The Win system driver is provided, and the directory is as follows:
Installation steps:
Run cmd as an administrator and
enter the command Bcdedit.exe -set TESTSIGNING ON to open the test mode:
after restarting the computer, the desktop shows that the test mode is running and the
driver is not installed. The device manager is as follows, Found a PCI serial port:
The compiled driver program provided by the routine is in the driver directory under the project (select the corresponding driver according to the operating system), and the
"xilinx PCIe driver related information" in the demo directory provides xilinx official Windows and linux driver source code and
test program, if you are interested, you can study it yourself:
select the device, right-click to update the driver,
browse the computer to find the driver software,
the test computer is installed with win7, here we use the Win7_Release version, and the win10 system is replaced with the Win10_Release version:
There is a security warning, choose to install:
the device driver is installed correctly
7. QT host computer software
QT Speed Measuring PC: provide source code and executable program, the released version is QT5.6.2; the location is as follows:
some source code screenshots are as follows:
8. Board debugging and verification
Open the host computer test program to test the PCIe speed, open the speed test software pciespeed in the figure below, the speed test software is in the following location
, the experimental results are as follows:
read and write at the same time test:
read-only test:
write-only test:
9. Welfare: acquisition of engineering code
Benefits: Obtaining the engineering code
The code is too large to be sent by email, and it is sent by a certain degree network disk link. The
method of data acquisition: private, or the V business card at the end of the article.
The network disk information is as follows:
