Table of contents
1 Introduction
PCIE (PCI Express) adopts the current popular point-to-point serial connection in the industry. Compared with the shared parallel architecture of PCI and earlier computer buses, each device has its own dedicated connection. It does not need to request bandwidth from the entire bus, and it can Improving the data transmission rate to a very high frequency and achieving the high bandwidth that PCI cannot provide is the preferred direction of high-speed interfaces in various industries at present, and has high practical value and learning value;
This design uses Xilinx's official XDMA solution to build a PCIE communication platform based on Xilinx series FPGAs. This solution is only applicable to Xilinx series FPGAs. It also provides XDMA installation drivers and QT host computer source codes, eliminating the need to use XDMA tedious drivers. I am at a loss for finding and developing PC software, and building a vivado project, saves the embarrassment of not knowing how to use XDMA, making the use of PCIE easy to use, without having to care about its complicated PCIE protocol; because I The development board only supports PCIE X4, so the code provided is PCIE X4 architecture. If you need friends with PCIE X1, X2, X8, X16, X32, you can modify this project by yourself, or follow me, I will release new projects in real time .
The basic PCIE speed test of this project has been modified, and the HDMI input interface that comes with the development board is used to collect HDMI input video in real time, output XDMA after buffering DDR3, and send it to the QT host computer display program through PCIE;
This article describes in detail the HDMI video acquisition design scheme based on XDMA to build PCIE. The project code can be compiled and debugged on the board, and can be directly transplanted. It is suitable for project development of students and graduate students, and also suitable for project development of on-the-job engineers. It can be applied It is used in the fields of high-speed interface and image transmission in medical, military and other industries;
it provides complete and smooth engineering source code and technical support;
the method of obtaining engineering source code and technical support is at the end of the article, please be patient to the end;
2. My existing PCIE solution
My homepage has a PCIE communication column, including PCIE solutions based on RIFFA and PCIE solutions based on XDMA; there are simple data interaction, speed measurement, and application-level image acquisition and transmission. The following is the address of the column: Click to go
directly
3. PCIE theory
For this part, you can learn theoretical knowledge from Baidu or csdn or Zhihu. In fact, XDMA is used, and there is no need for complex protocols and theories until PCIE. . .
4. Overall design idea and plan
The overall design idea and scheme are as follows:
The PCIe communication routine consists of three parts: FPGA-side program, PCIe card driver, and PCIe host computer test program:
FPGA-side project: responsible for establishing the FPGA framework required for communication with PCIe, and the construction of the PCIe communication protocol ;
PCIe driver: responsible for the data exchange between the host computer test program and the PCIe card;
PCIe host computer test program: PCIe display here;
Video input: Laptop analog HDMI video input source;
HDMI decoding, using silicon9134 chip to complete HDMI decoding, silicon9134 needs i2c configuration to use, about the use of silicon9134 i2c configuration, please refer to my previous article: click to go directly to image
cache: using AXI4 The bus realizes the image reading and writing DDR3, and 3 frame buffers are made here;
output: PCIE X4;
QT speed measurement host computer: provide source code and executable program, and the development version is QT5.6.2;
5. Detailed explanation of vivado project
Development board FPGA model: Xilinx xc7a100tfgg484-2;
development environment: Vivado2019.1;
input: HDMI;
output: PCIE X4;
application: QT host computer display test;
project BD is as follows:
the integrated project code structure is as follows:
after comprehensive compilation The estimated FPGA resource consumption and power consumption are as follows:
6. Driver installation
Provide Win system driver, the directory is as follows:
Driver installation refers to the previous speed test: click to go directly
7. QT host computer software
QT display host computer: provide source code and executable program, the released version is QT5.6.2; the location is as follows:
some source code screenshots are as follows:
8. Board debugging and verification
Open the host computer test program for PCIe display test, open the display software pcie2screen shown in the figure below, the software is in the following location, the experimental results are as follows: After turning on the
host computer, you can see that the software pauses playback:
click the middle button to start playing HDMI input video source video:
9. Welfare: acquisition of engineering code
Benefits: Obtaining the engineering code
The code is too large to be sent by email, and it is sent by a certain degree network disk link. The
method of data acquisition: private, or the V business card at the end of the article.
The network disk information is as follows:
