Table of contents
1 Introduction
At present, there are many implementation schemes of USB2.0, but from the perspective of simplicity and ease of use, Cypress’s CY7C68013A should be the best scheme, because it integrates 8051 CPU inside and encapsulates it as a FIFO interface, the circuit design is simple, and the operation sequence is simple. The software driver is simple, and the official even provides a wealth of driver source code and test software including FPGA drivers;
This design uses FPGA to drive Cypress's CY7C68013A chip to realize USB2.0 video capture and transmission test, using SlaveFIFO mode communication, we provide CY7C68013A configuration firmware and source code, general firmware source code does not need to be modified, just download it directly through official tools, official We also provide tools and put them in the data package; based on the video transmission test of the SlaveFIFO interface, the FPGA development board collects the OV5640 camera data in real time, uses a FIFO buffer and cross-clock domain processing, and then sends the image data to the CY7C68013A chip , send it to the computer through the USB2.0 interface, and the upper computer on the computer side receives and displays the output; after the code is compiled and passed the debugging and verification on the board, it can be directly transplanted to the project. Engineers do project development, which can be applied to the fields of USB2.0 communication and image transmission in medical, military and other industries;
provide complete and smooth engineering source code and technical support;
how to obtain engineering source code and technical support, as well as demonstrations of on-board debugging The video is at the end of the article, please be patient to see the end;
2. The FPGA USB communication solution that I have here
My existing FPGA here is based on CY7C68013A's USB3.0 communication solution, which mainly includes data loopback test, picture sending and receiving test, video sending and receiving test, video sending and receiving is based on OV5640 camera; if you are interested, you can go to my USB2.0 communication column to read, The column address is as follows:
Click to go directly to the column
In addition, the FPGA I have here is based on the FT601 and FT602 USB3.0 communication solutions, which mainly include simple speed measurement solutions and image transmission solutions. The image transmission solutions include simple color bar transmission and acquisition, OV5640 camera transmission and acquisition, and HDMI video acquisition. HDMI video capture and capture, USB3.0 UVC video, etc., all engineering solutions include FPGA engineering and QT host computer source code; those who are interested can go to my FT601 USB3.0 communication column to read, the column address is as follows: click to go directly to the
column
3. CY7C68013A chip interpretation and hardware design
Introduction to FX2
Cypress's EZ-USB FX2 is the world's first integrated USB2.0 microprocessor, which integrates a USB2.0 transceiver, SIE (Serial Interface Engine), an enhanced 8051 microcontroller and a programmable peripheral interface. This ingenious structure of FX2 enables the data transmission rate to reach 480MBit/s. In FX2, the intelligent SIE can handle many USB1.1 and USB2.0 protocols in hardware, thereby reducing development time and ensuring USB compatibility. The device has the following features:
1: Embedded 480MBit/s transceiver, phase-locked loop PLL, serial interface engine SIE—integrates the
physical layer of the entire USB 2.0 protocol.
2: Built-in enhanced 8051 that can work at 48MHz, the 8051 controller has the following features:
(1) It has 256Byte register space, two serial ports, three timers, and two data pointers.
(2) Four machine cycles (83.3ns when working at 48MHz) constitute one instruction cycle.
(3) Special function registers (including I/O port control registers) can be accessed at high speed.
(4) The application of USB vector interrupt has extremely short ISR response time.
(5) It is only used for USB transaction management and control, and does not participate in data transmission, which better solves the
bandwidth problem of USB high-speed mode.
3: "Soft configuration" - the USB firmware can be downloaded from the USB bus, no need to integrate ROM on the chip.
4: It has four FIFO interfaces and can work under internal or external clock. The application of endpoint and FIFO interface enables
high-speed connection between external logic and USB bus.
5: A single-chip USB 2.0 peripheral solution that does not require an external protocol physical layer. FX2 integrates all functions
on one chip.
A typical FX2 controller, such as the internal structure of CY7C68013A is as follows:
SlaveFIFO mode and its configuration
The FX2-FPGA interface provides a very simple-to-use interface for FPGA-based applications implementing high-speed USB connectivity such as data acquisition, industrial control and monitoring, and image processing. FX2 operates in SlaveFIFO mode, FPGA is used as the master device.
SlaveFIFO: In this mode, an external system connected to FX2 can generate read and write control signals, so it can act as a master device for FX2. In FPGA-based applications, FX2 is generally configured as SlaveFIFO mode. The figure below is the system block diagram when FX2 connects with external FPGA through slave device FIFO interface.
In this way, the function of 8051 firmware embedded in FX2 is only to configure Slave FIFO related registers and control when FX2 works in Slave FIFO mode. Once the 8051 firmware configures the relevant registers and makes itself work in the Slave FIFO mode, the external logic (such as FPGA) can communicate with the host at high speed according to the transmission timing of the Slave FIFO, and the 8051 is not needed during the communication process. Firmware involvement. The configuration of SlaveFIFO mode needs to install a set of official tools provided by CY7C68013A to download relevant firmware to complete. I have packaged this set of things, and specially wrote a document for tool installation, driver installation, tool use, and firmware download, and put it together. In the data package, as follows:
The figure below is a schematic diagram of the connection between FX2 and FPGA in SlaveFIFO mode.
The specific signal pins are described as follows.
For the IFCLK signal, it is a direction-configurable signal, which can be output by FX2 and connected to an external device such as FPGA, or configured as an input to receive a clock signal from an external device. In this example, configure IFCLK as an output. That is, it is output to FPGA by FX2 as a synchronous clock for data and control signals.
4. Detailed engineering design plan
The detailed design scheme is as follows:
The FPGA development board collects the data of the OV5640 camera in real time. The OV5640 camera needs i2c configuration to be used. This design provides the i2c configuration module of verilog to complete the i2c configuration of the OV5640 camera, a FIFO buffer and cross-clock domain processing, and then the The image data is sent to the CY7C68013A chip, and sent to the computer through the USB2.0 interface, and the host computer on the computer receives and displays the output;
5. vivado project
Development board FPGA model: Xilinx-XC7A35T-2FGG484C-2;
development environment: vivado2019.1;
input: OV5640 camera;
output: host computer display; application
: USB2.0 interface image transmission ; FPGA resource consumption and power consumption are estimated as follows:
6. Board debugging and verification
Power on the board first, and then download the CY7C68013A firmware. Generally, the firmware only needs to be downloaded once, because the schematic design of CY7C68013A usually has an external e2prom; download the FPGA bit stream, and open the output effect of the host computer software, as follows:
7. Welfare: acquisition of engineering code
Benefits: Obtaining the engineering code
The code is too large to be sent by email, and it is sent by a link to a certain network disk.
Data acquisition method 1: private, or the V business card at the end of the article.
The network disk information is as follows:
