FPGA collects AD7606 data UDP network transmission Provides engineering source code and technical support with upper computer receiving software

1 Introduction

At present, the basic ecology of udp implemented by fpga on the Internet is as follows:
1: udp transceiver written in verilog, but without ping function, such code function can be used normally, but without ping function, it is basically waste, and will not be used in actual projects Such a code, just imagine, multi-machine interconnection, if there is a problem, your network card does not have a ping function, and you don’t even have a basic troubleshooting mechanism. Who would dare to use such a code?
2: The udp transceiver with ping function, the code is excellent and easy to use, but it is basically not open source, and the source code will not be provided to you. This kind of code also has shortcomings, that is, if there is a problem, I don’t know how to troubleshoot it. ;
3: Using Xilinx's triple-speed network IP implementation, this kind of code is also very good, but there is still the same problem, there is no source code, and the triple-speed network IP needs a license, the official license is only valid for 120 days, in fact, the triple-speed network IP Only the conversion from rgmii to gmii and then to axis is realized, and this ip is completely unnecessary; the
UDP solution used in this design uses Micrel's KSZ9031RNX as the network PHY chip, uses verilog code to design the UDP protocol, and has a user interface, so that users do not need to Concerned about the complex UDP protocol and only need to care about the simple user interface timing to operate UDP sending and receiving, very simple;

This design uses UDP to transmit AD7606 data collected by FPGA, and the host computer displays the waveform data of AD7606 on the computer by receiving the UDP data packet from the network port. We can observe the waveform in a more intuitive way, which is a prototype of a digital oscilloscope and can save ADC data.

2. The UDP scheme I have here

At present, I have the following UDP solutions and application examples:
My blog homepage has a FPGA Ethernet communication column, which is free, and there are many UDP applications implemented by FPGA. Brothers who need network communication can go and have a look : Click directly to go to

3. Detailed explanation of AD7606 acquisition

The output of AD7606 has two modes: serial and parallel. If you want to play with AD7606, you must first read the data sheet. When designing the interface based on the data sheet, I have both serial mode and parallel mode acquisition. I have written it before. An article explained in detail, brothers can look back at my article first, to lay the foundation: click directly to go

4. UDP design scheme

This experiment takes Gigabit Ethernet RGMII communication as an example to design a verilog program. UDP is divided into two parts, namely sending and receiving, and realizes dynamic ARP, UDP, Ping and 10/100/1000M network speed automatic negotiation and arbitration functions. The following is the block diagram of the principle implementation: For detailed design, please refer to the article I wrote before: Click directly to go

5. Detailed design scheme of AD7606 UDP transmission

The detailed design scheme of AD7606 UDP transmission is as follows:

Use an oscilloscope to generate a sine wave as the input source to AD7606. AD7606 data acquisition supports parallel and serial modes, which are integrated in the top-level file of the project code, as follows: The collected AD data is sent

to DDR3 cache, this data cache module can not only cache AD data, but also cache image data, and has a 4-frame cache mode, because this design mainly introduces the UDP package, so the data cache module will not be introduced too much, if you are interested You can view the detailed source code.

Design ideas for UDP applications

UDP itself is just a communication protocol, and it is not difficult to implement it with verilog. Its essence lies in the application, and the key point of UDP application lies in the packaging and unpacking of data. The data is assembled and unpacked, and the unpacking is done by the host computer software.
Notice! ! !
The grouping here refers to the artificial grouping of the UDP valid data segment in the Ethernet frame format, not the grouping of the fixed frame header and other information in the UDP protocol. The grouping here is for the sending and receiving correspondence between two nodes. . .
After the communication starts, the upper computer sends a query command to the FPGA, and the FPGA sends the basic information of the local network card and the data information of the AD7606 to the upper computer. Send data to the upper computer according to the UDP data packet defined by yourself, so that a simple UDP communication application is completed. . .
The design package agreement is as follows:

Obtain FPGA network card information

The query command (5 bytes in total, sent by the host computer via Ethernet)

and the response command (27 bytes in total, sent by the development board via Ethernet)

code level are as follows: (eth_cmd.v)

retrieve data

Control command (data request sent by host computer)

each UDP packet contains Header, in the first byte, its format is as follows:

UDP sends data packets

Notice! ! !
Notice! ! !
Notice! ! !
This is the key point of the whole project. The data of AD7606 is sent out in this format: the

code level is as follows: (mac_ctrl.v)

UDP sending process

First of all, in the idle state, the host machine sends inquiry commands through Ethernet broadcast, so when receiving at the IP layer, it is necessary to judge whether it is broadcast UDP data, and if so, also receive data. This code is in ip_rx.v, as shown below :

Then judge whether the received data information is an inquiry command or a control command in the eth_cmd.v file, so as to generate the
command response request signal cmd_reply_req or the data request signal ad_data_req.
The top-level interface of the eth_cmd.v module is as follows:

The mac_ctrl.v file implements Ethernet transmission control, waits for a certain period of time in the IDLE state, enters the CMD_WAIT state, and judges whether there is a command request cmd_reply_req or data request ad_data_req, and then enters the CHECK_ARP state to check
the corresponding Whether the IP address of the user is in the cache list, if not, it will send an ARP request and wait for the response. Then enter the corresponding data sending state according to the command request or data request, CMD_SEND or AD_SEND state.
The top-level interface of the mac_ctrl.v module is as follows:

the cache space set by the host computer is 1M bytes, and the request data interval is 100ms, so these two points should be considered when setting the sampling depth. In the eth_top.v program, it is set to 32'h00008000, which is 32K bytes, the sampling frequency is 200KHz, and the data at the sampling end of the ADC is two bytes long, so the sampling length is the sampling byte divided by 2, which is 32'h00004000, calculated It takes 82ms to complete the acquisition. Removed checksum for UDP send data.
The code level is as follows: (eth_top.v)

6. Detailed explanation of vivado project

Project introduction:
Development board: Xilinx Artix7 development board;
development environment: vivado2019.1;
network PHY: KSZ9031;
input: AD7606;
output: UDP-RJ45 network port;
the project code structure is as follows:

FPGA resource consumption and power consumption estimates are as follows:

7. Board debugging verification and demonstration

The position of the host computer software is as follows:

When the host computer does not receive data, it is as follows:

Use an oscilloscope to generate a 5V sine wave and connect it to the AD7606 adapter board. The actual waveform of the host computer is as follows: the

green box shows the MAC and IP address of the sending board;
reset: Click reset to make the waveform display to the initial state;
vertical: switch between "vertical" and "horizontal", click this button to switch between horizontal and vertical zooming, in the vertical state, roll the mouse roller to zoom in the vertical direction, horizontal In the state, zoom in the horizontal direction;
pause: switch between "pause" and "continue", click to pause the waveform, and then click "continue" to display the waveform;
save: save the ADC data as a TXT file, and the save path is at the "path" button Setting, the default is the path where the software is located;
value: switch between "value" and "voltage", the coordinate unit in the Y direction is the original value, that is, the received original data value, click "voltage" to display the voltage value; path: select the save path
;
Open: Open the saved TXT wave file;

8. Benefits: Acquisition of engineering codes

Benefits: Obtaining the engineering code
The code is too large to be sent by email, and it is sent by a certain degree network disk link. The
method of data acquisition: private, or the V business card at the end of the article.
The network disk information is as follows: