Table of contents
1 Introduction
At present, there are many implementation schemes of USB3.0, but from the point of view of simplicity and ease of use, FT601 should be the best scheme, because of its simple circuit design, simple operation sequence, simple software driver, and the official even provides FPGA driver. Rich driver source code and test software;
This design uses FPGA to drive FT601 chip to realize USB3.0 data communication, uses synchronous 245 mode communication, provides vivado project source code, uses laptop computer to simulate HDMI camera, HDMI video is input to FPGA development board onboard ADV7611 decoding chip, and HDMI video is decoded For RGB video, FPGA reads out the RGB video data after three frames of image buffering to DDR3, the image is sent to FT601, the PC reads the video sent by FT601, and uses the QT host computer to receive and display the video; this design is
completely It can simulate and realize the function of USB3.0 camera; after the code is compiled and passed the debugging and verification on the board, it can be directly transplanted to the project. The field of USB3.0 communication and image transmission in medical, military and other industries;
provide complete and smooth engineering source code and technical support;
the acquisition method of engineering source code and technical support and the demonstration video of board debugging are at the end of the article, please be patient until the end;
2. FT601 chip interpretation and timing analysis
FT601 function and hardware circuit
The technical parameters of FT600/601Q are as follows:
FT600&601Q chip is the latest USB3.0 to FIFO interface IC released by FT, which realizes data transmission between USB3.0 and 16/32bit parallel IO interface.
The entire USB communication protocol is completed by the chip driver itself, and the developer does not need to consider the programming of the USB underlying firmware.
Compatible with USB3.0 (5Gbps), backward compatible with USB2.0 (480Mbps and 12Mbps) transmission.
Up to 8 configurable Endpoints. >>Support 2 kinds of FIFO transmission protocols, the maximum transmission can reach 400MB/s.
There is a buffer of 16K bytes inside the chip, which can perform high-throughput operations on data.
Support remote wake-up function.
The chip supports multiple IO voltages: 1.8V, 2.5V, 3.3V.
Through 16bit D[O: 15] or 32bit D[0:31] parallel data lines and read/write status/control lines RXF, TXE, RD, WR, plus the clock CLK, enable the OE signal line to achieve communication with the CPU
/ FPGA data exchange.
The chip integrates 1.0V LDO, which can be used for the core part of the chip.
Industrial grade chips, operating temperature range -40 to 85°C.
The chip framework is as follows:
the peripheral circuit design reference is as follows:
FT600/601Q supports multiple transmission modes, among which 245 Synchronous FIFO mode and Multi-Channel FIFO mode are our most commonly used modes. The demo we introduce here takes the 245 Synchronous FIFO mode as an example; the transmission mode is configured through the high and low levels of the GPIO pin, and the configuration truth table is as follows:
Interpretation of FT601 read timing
245 Synchronous FIFO mode read timing is as follows:
RXF_N is the read data status signal, FPGA can read FT601 data when RXF_N is low level; after
detecting RXF_N low level, pull down OE_N and RD_N, and then start reading data;
RXF_N is detected After the high level, pull up OE_N and RD_N, and then exit the read data state;
Interpretation of FT601 write timing
245 Synchronous FIFO mode write timing is as follows: TXF_N
is the status signal for reading data, and RXF_N is the low level period when FPGA writes data to FT601
;
After TXF_N is high, pull WR_N high, and then exit the state of writing data;
3. My FT601 USB3.0 communication solution here
The existing FPGA USB3.0 communication scheme based on FT601 and FT602 here mainly includes simple speed measurement scheme and image transmission scheme. The image transmission scheme includes simple color bar transmission collection, OV5640 camera transmission collection, HDMI video collection, HDMI video collection Snapshot, USB3.0 UVC video, etc., all engineering solutions include FPGA project and QT host computer source code; those who are interested can go to my FT601 USB3.0 communication column to read, the column address is as follows: https://blog.csdn
. net/qq_41667729/category_12339160.html?spm=1001.2014.3001.5482
4. Detailed design plan
The detailed design block diagram is as follows:
HDMI video input and capture:
Use a laptop to simulate an HDMI camera, and input the HDMI video to the ADV7611 decoder chip on the FPGA development board to decode the HDMI video into RGB video. The ADV7611 decoder chip needs i2c configuration to use. The i2c configuration of pure verilog code is provided in the routine;
FDMA image cache:
FDMA image three-frame cache, brothers who often read my articles know that this is my usual image cache routine, which is composed of FDMA controller and FDMA. It is to cache the input video in DDR3 for three frames and then read it out. The purpose is to make the input and output of the image data read and write across the clock domain, and the output image is stable without tearing. For the detailed design description of FDMA, please refer to My previous article: Click to go directly to
FT601 Module:
It is the verilog driver code of FT601. It is very simple to realize the interface connection according to the read and write timing of the FT601 chip; for detailed design instructions of the FT601 driver, please refer to my previous article: Click to go directly
FT601 driver:
This is the official FT601 driver, the file has been included in the data package I provided;
QT host computer:
QT based on c++, call the official API, realize real-time acquisition and display of video data of USB3.0 interface, I The provided information package contains QT host computer software and QT source code, which can be used for reference by brothers who do embedded software development;
5. Detailed explanation of vivado project
Development board FPGA model: xc7k325tffg900-2;
development environment: vivado2022.2;
input: HDMI;
output: FT601–USB3.0 interface;
application: simulate and realize the function of USB3.0 camera;
The project Block Design is as follows:
The integrated project code structure is as follows:
The estimated FPGA resource consumption and power consumption after comprehensive compilation are as follows:
6. Board debugging and verification
First connect the board and computer, then open the QT host computer software, the directory in the data package is as follows:
QT receiving result:
7. Welfare: acquisition of engineering code
Benefits: Obtaining the engineering code
The code is too large to be sent by email, and it is sent by a link to a certain network disk.
Data acquisition method 1: private, or the V business card at the end of the article.
The network disk information is as follows:
