zynq implements PCIE X8 video capture card based on XDMA to provide engineering source code and QT host computer program and technical support

1 Introduction

PCIE (PCI Express) adopts the current popular point-to-point serial connection in the industry. Compared with the shared parallel architecture of PCI and earlier computer buses, each device has its own dedicated connection. It does not need to request bandwidth from the entire bus, and it can Improving the data transmission rate to a very high frequency and achieving the high bandwidth that PCI cannot provide is the preferred direction of high-speed interfaces in various industries at present, and has high practical value and learning value;

This design uses Xilinx's official XDMA solution to build a PCIE communication platform based on Xilinx series FPGAs. This solution is only applicable to Xilinx series FPGAs. It also provides XDMA installation drivers and QT host computer source codes, eliminating the need to use XDMA tedious drivers. I am at a loss for finding and developing PC software, and building a vivado project, saves the embarrassment of not knowing how to use XDMA, making the use of PCIE easy to use, without having to care about its complicated PCIE protocol; because I The development board only supports PCIE X8, so the code provided is PCIE X8 architecture. If you need friends with PCIE X1, X2, X8, X16, X32, you can modify this project by yourself, or follow me, I will release new projects in real time .
This project realizes the basic PCIE communication, and conducts a speed test with the QT host computer.

This article describes in detail the design scheme of zynq to build a PCIE communication platform based on XDMA. Using the HDMI input and output interfaces that come with the development board, the function of the PCIE video capture card is realized. The FPGA development board collects and inputs HDMI video in real time, and all the way through DDR buffer The HDMI output interface is output to the display, and the other channel is output to the computer through XDMA through PCIE after being buffered by DDR. The QT host computer of the computer displays the HDMI input video in real time; different from the pure FPGA project released before, this design is based on the zynq architecture PCIE project; the project code can be comprehensively compiled and debugged on the board, and can be directly transplanted. It is suitable for project development of students and graduate students, and also suitable for project development of in-service engineers. It can be applied to high-speed interface fields in medical, military and other industries;
provide Complete and smooth project source code and technical support;
the way to obtain project source code and technical support is at the end of the article, please be patient to the end;

2. My existing PCIE solution

My homepage has a PCIE communication column, which includes PCIE solutions based on RIFFA and PCIE solutions based on XDMA; there are simple data interaction, speed measurement, and application-level image acquisition and transmission, as well as pure FPGA-based PCIE projects , there is also a PCIE project based on the zynq architecture, the following is the column address:
Click to go directly

3. PCIE based on zynq architecture

For the theoretical part of PCIE, you can learn theoretical knowledge from Baidu or csdn or Zhihu. In fact, XDMA is used, and there is no need for complex protocols and theories until PCIE. . .
Here we will focus on the PCIE design method based on the zynq architecture;
we know that for data interaction between PCIE and the PC, the DDR memory attached to the FPGA must be used as an "intermediary"; but the FPGA of the zynq architecture has a characteristic, its PL and DDR can be installed on the PS side, so can the DDR on both sides be used as the "intermediary" of PCIE communication? Obviously, it is impossible to have both fish and bear's paws;
let's take a look at the HP bus of zynq first. The highest bit width of HP is only 64 bits, as follows:

If the reference clock given by zynq to PL is 150M, then the total bandwidth of HP is 150000000x64=9.6 Gb; even if the reference clock is increased to an astonishing 200M, then the total bandwidth of HP is 200000000x64=12.8Gb; while the PCIE2.0 single Line speed of XDMA is 5Gb, and the total speed of PCIEX8 is 5x8=40Gb; It is impossible for PS side DDR as the "intermediary" of PCIE and PC communication to meet the loan requirements. In addition, due to coding, protocol and other expenses, the available bandwidth can only reach 80%, and PS side DDR is even more impossible, so we can only choose PL The side DDR is used as the "intermediary" of PCIE and PC communication;
let's see why the PL side DDR can:
PL side calls MIG, the user operation clock of MIG is 200M, and the AXI data bit width is 256 bits, so the theoretical bandwidth=200000000x256=51.2 Gb; actual bandwidth = 51.2x80% = 40.96Gb; just enough to meet the 40Gb line rate of PCIEX8 2.0;
such a detailed calculation tells you the reason for choosing the PL side DDR of zynq, which is enough for nanny-level teaching. . .

4. Overall design idea and scheme

The overall design idea and scheme are as follows:

Video input path

The notebook simulates the HDMI video source, and there is a silicon9013 decoding chip on board to decode the differential HDMI video into RGB data. The silicon9013 is configured by zynq's i2c, and there is a configuration part of the source code in the provided SDK code; calling Xilinx official video in to AXIS will The RGB video stream is converted to an AXIS video stream, and the HDMI video is buffered to the DDR3 on the PL side via VDMA; here, VDMA_0 is configured as write-only mode;

Video output path

VDMA_1 is configured in read-only mode, reads out the cached video, calls AXIS to video out to convert the AXIS video stream from VTC to VGA timing video stream, and has an ADV7511 encoding chip on board to encode the RGB data of the VGA video stream It is a TMDS differential video output display; ADV7511 is configured by zynq's i2c;

PCIE output host computer path

Call Xilinx official XDMA to realize PCIE communication, XDMA directly reads the HDMI video buffered in DDR3 through the AXI bus, and then sends the read video to the computer through the onboard PCIE X8 connector, and the QT host computer program on the computer side calls XDMA official API Realize the real-time display of the collected video; the data package provides the exe executable file of the QT host computer and the c++ source code of the QT host computer;

5. Detailed explanation of vivado project

Development board FPGA model: Xilinx–zynq–xc7z100ffg900-2;
development environment: Vivado2019.1;
input: HDMI; silicon9013 decoding;
output 1: HDMI; ADV7511 encoding;
output 2: XDMA; PCIE X8;
application: QT host computer display test ;
The project BD is as follows:




the integrated project code structure is as follows:

the estimated FPGA resource consumption and power consumption after comprehensive compilation is as follows:

6. Detailed explanation of SDK project

The SDK mainly completes the i2c configuration of the HDMI codec chip, the register configuration of the VDMA, the configuration of the VTC, etc. The SDK part is implemented in C language, and the code structure is as follows:

7. Driver installation

Provide Win system driver, the directory is as follows:

Provide Win and Linux driver,
please refer to my previous article for the specific installation tutorial of the driver: Click to go directly

8. QT host computer software

QT speed measuring host computer: provide source code and executable program, the released version is QT5.6.2; the location is as follows:

9. Board debugging and verification

Open the host computer test program for PCIe display test, open the display software pcie2screen shown in the figure below, the software is in the following location, the experimental results are as follows: After turning on the

host computer, you can see that the software pauses playback:

click the middle button to start playing HDMI input video source video:

10. Welfare: acquisition of engineering code

Benefits: Obtaining the engineering code
The code is too large to be sent by email, and it is sent by a certain degree network disk link. The
method of data acquisition: private, or the V business card at the end of the article.
The network disk information is as follows: