Table of contents
1 Introduction
PCIE (PCI Express) adopts the current popular point-to-point serial connection in the industry. Compared with the shared parallel architecture of PCI and earlier computer buses, each device has its own dedicated connection, does not need to request bandwidth from the entire bus, and can increase the data transmission rate to a very high frequency, reaching the high bandwidth that PCI cannot provide. It is the preferred direction of high-speed interfaces in various industries at present, and has high practical value and learning value;
This design uses Xilinx’s official XDMA solution to build a PCIE3.0 communication platform based on Xilinx series FPGAs. The QT host computer captures the screen pictures of the computer desktop in real time. My computer’s resolution is 1920X1080. The QT software will send the pictures to the PCIE bus, and the XDMA driver will send the data on the PCIE bus. After receiving the interrupt signal from XDMA, the FDMA controller reads the picture from DDR4, then puts the image information into the VGA timing data bus to form a VGA timing video stream, and sends the video stream to the HDMI sending module to convert the RGB data into HDMI differential data and output it to the display through the HDMI cable;
The key to this design is that we have written an XDMA interrupt module of xdma_inter.v. This module is used to cooperate with the driver to handle interrupts. xdma_inter.v provides an AXI-LITE interface. The host computer reads and writes the registers of xdma_inter.v by accessing the user space address. The module registers the interrupt bit number in the interrupt bit input by user_irq_req_i, and outputs it to XDMA IP. When the driver of the upper computer responds to the interrupt, write the xdma_inter.v register in the interrupt to clear the processed interrupt.
This solution is only applicable to Xilinx series FPGAs. It also provides XDMA installation drivers and QT host computer source codes, which saves the cumbersome driver search using XDMA and the confusion of host computer software development, and builds a vivado project. It saves the embarrassment of not knowing how to use XDMA, making the use of PCIE easy to use, and you don’t need to care about its complicated PCIE protocol; since my development board only supports PCIE X8, the code provided is PCIE X8 architecture. If you need PCIE X1, Friends of X2, X8, X16, and X32 can modify this project by themselves, or follow me, and I will release new projects in real time.
This project implements PCIE communication for advanced applications, and conducts video transmission tests with QT host computer. This article describes in detail the design scheme of building a PCIE communication platform based on XDMA. The engineering code can be comprehensively compiled and debugged on the board, and can be
directly ported to the project. It is suitable for project development by students and graduate students, as well as for on-the-job engineers .
2. My existing PCIE solution
There is a PCIE communication column on my homepage, which implements data interaction with QT host computer based on XDMA polling mode. There are both PCIE solutions based on RIFFA and PCIE solutions based on XDMA. There are simple data interaction, speed measurement, and application-level image acquisition and transmission. : Click to go
directly to
3. PCIE theory
For this part, you can learn theoretical knowledge from Baidu or csdn or Zhihu. In fact, XDMA is used, and there is no need for complex protocols and theories until PCIE. . .
4. Overall design idea and scheme
The overall design idea and scheme are as follows:
Image generation, sending, caching
The QT host computer captures the screen picture of the computer desktop in real time. The resolution of my computer is 1920X1080. The QT software will send the picture to the PCIE bus, and the XDMA driver will send the data on the PCIE bus; the XDMA IP core of the FPGA development board will cache the received picture data to DDR4, and notify the user to read out the picture data cached in DDR3 by means of an interrupt;
Introduction to XDMA
The DMASubsystem for PCIExpressIP provided by Xilinx is a high-performance, configurable SG mode DMA suitable for PCIE2.0 and PCIE3.0, providing user-selectable AXI4 interface or AXI4-Stream interface. Generally, the AXI4 interface can be added to the system bus interconnection, which is suitable for asynchronous transmission of large amounts of data. Usually, DDR is used, and the AXI4-Stream interface is suitable for low-latency data stream transmission.
XDMA is SGDMA, not Block DMA. In SG mode, the host will form the data to be transmitted in the form of a linked list, and then send the first address of the linked list to XDMA through BAR. XDMA will complete the transmission tasks specified by the linked list in turn according to the first address of the linked list structure. The XDMA block diagram is as follows: AXI4, AXI4-Stream, one must be selected for data transmission AXI4-Lite Master is optional, used to implement PCIE BAR address to AXI4-lite Mapping of register addresses, which can be used to read and write user logic registers
.
AXI4-Lite Slave is optional and is used to open the XDMA internal registers to user logic. User logic can access XDMA internal registers through this interface and will not be mapped to BAR.
AXI4 Bypass interface, optional, used to implement PCIE pass-through user logic access, which can be used for low-latency data transmission.
XDMA interrupt mode
The key to this design is that we have written an XDMA interrupt module of xdma_inter.v. This module is used to cooperate with the driver to handle interrupts. xdma_inter.v provides an AXI-LITE interface. The host computer reads and writes the registers of xdma_inter.v by accessing the user space address. The module registers the interrupt bit number in the interrupt bit input by user_irq_req_i, and outputs it to XDMA IP. When the driver of the upper computer responds to the interrupt, write the xdma_inter.v register in the interrupt to clear the processed interrupt.
In addition, in this program, AXI-BRAM is used to demonstrate the read and write access test of the user space.
Image reading, output, display
After receiving the interrupt signal from XDMA, the FDMA controller reads the picture from DDR4, and then puts the image information into the VGA timing data bus to form a VGA timing video stream, and then sends the video stream to the HDMI sending module to convert the RGB data into HDMI differential data and output it to the display through the HDMI cable; the VGA timing resolution is 1920X1080@60Hz; for the detailed design description of FDMA, please refer to my previous article: click to go directly
QT host computer and its source code
QT host computer This solution uses VS2015 + Qt 5.12.10 to complete the development software environment of the host computer. The QT program calls the official XDMA API to realize data interaction with the FPGA in interrupt mode. This routine implements reading and writing speed, and provides QT host computer software and its source code. The path is as follows: The screenshot of the QT source code part is as follows
:
5. Detailed explanation of vivado project
Development board FPGA model: Xilinx–xcku060-ffva1156-2-i;
development environment: Vivado2022.2; input : QT host computer captures
the computer screen with a resolution of 1920X1080;
output: HDMI with a resolution of 1920X1080@60Hz ; The number of interrupts is also set to 4, as follows: The code structure after synthesis is as follows : The estimated FPGA resource consumption and power consumption after comprehensive compilation are as follows:
6. Board debugging and verification
Run the QT software to capture the computer screen picture, and the fpga development board receives the picture and outputs it to the display. The experimental results are as follows:
7. Welfare: acquisition of engineering code
Benefits: Obtaining the engineering code
The code is too large to be sent by email, and it is sent by a certain degree network disk link. The
method of data acquisition: private, or the V business card at the end of the article.
The network disk information is as follows:
