zynq implements PCIE X8 video capture HDMI output based on XDMA Provides engineering source code and QT host computer program and technical support

1 Introduction

PCIE (PCI Express) adopts the current popular point-to-point serial connection in the industry. Compared with the shared parallel architecture of PCI and earlier computer buses, each device has its own dedicated connection. It does not need to request bandwidth from the entire bus, and it can Improving the data transmission rate to a very high frequency and achieving the high bandwidth that PCI cannot provide is the preferred direction of high-speed interfaces in various industries at present, and has high practical value and learning value;

This design uses Xilinx's official XDMA solution to build a PCIE communication platform based on Xilinx series FPGAs. This solution is only applicable to Xilinx series FPGAs. It also provides XDMA installation drivers and QT host computer source codes, eliminating the need to use XDMA tedious drivers. I am at a loss for finding and developing PC software, and building a vivado project, saves the embarrassment of not knowing how to use XDMA, making the use of PCIE easy to use, without having to care about its complicated PCIE protocol; because I The development board only supports PCIE X8, so the code provided is PCIE X8 architecture. If you need friends with PCIE X1, X2, X8, X16, X32, you can modify this project by yourself, or follow me, I will release new projects in real time .
This project realizes the basic PCIE communication, and conducts a speed test with the QT host computer.

This article describes in detail the design scheme of zynq to build a PCIE communication platform based on XDMA. Using the HDM output interface that comes with the development board, the function of the PCIE video capture card is realized. Send the real-time image to the FPGA board, the FPGA board receives the image from PCIE through XDMA, and writes the image into the DDR3 buffer, zynq configures VDMA to read the image from DDR3, and then outputs the image to the monitor through AXIS to video out ;Different from the previous pure FPGA project, this design is a PCIE project based on the zynq architecture; the project code can be comprehensively compiled and debugged on the board, and can be directly transplanted. Project development, which can be applied to high-speed interface fields in medical, military and other industries;
provide complete and smooth engineering source code and technical support;
the method of obtaining engineering source code and technical support is at the end of the article, please be patient to the end;

2. My existing PCIE solution

My homepage has a PCIE communication column, which includes PCIE solutions based on RIFFA and PCIE solutions based on XDMA; there are simple data interaction, speed measurement, and application-level image acquisition and transmission, as well as pure FPGA-based PCIE projects , there is also a PCIE project based on the zynq architecture, the following is the column address:
Click to go directly

3. PCIE based on zynq architecture

For the theoretical part of PCIE, you can learn theoretical knowledge from Baidu or csdn or Zhihu. In fact, XDMA is used, and there is no need for complex protocols and theories until PCIE. . .
Here we will focus on the PCIE design method based on the zynq architecture;
we know that for data interaction between PCIE and the PC, the DDR memory attached to the FPGA must be used as an "intermediary"; but the FPGA of the zynq architecture has a characteristic, its PL and DDR can be installed on the PS side, so can the DDR on both sides be used as the "intermediary" of PCIE communication? Obviously, it is impossible to have both fish and bear's paws;
let's take a look at the HP bus of zynq first. The highest bit width of HP is only 64 bits, as follows:

If the reference clock given by zynq to PL is 150M, then the total bandwidth of HP is 150000000x64=9.6 Gb; even if the reference clock is increased to an astonishing 200M, then the total bandwidth of HP is 200000000x64=12.8Gb; while the PCIE2.0 single Line speed of XDMA is 5Gb, and the total speed of PCIEX8 is 5x8=40Gb; It is impossible for PS side DDR as the "intermediary" of PCIE and PC communication to meet the loan requirements. In addition, due to coding, protocol and other expenses, the available bandwidth can only reach 80%, and PS side DDR is even more impossible, so we can only choose PL The side DDR is used as the "intermediary" of PCIE and PC communication;
let's see why the PL side DDR can:
PL side calls MIG, the user operation clock of MIG is 200M, and the AXI data bit width is 256 bits, so the theoretical bandwidth=200000000x256=51.2 Gb; actual bandwidth = 51.2x80% = 40.96Gb; just enough to meet the 40Gb line rate of PCIEX8 2.0;
such a detailed calculation tells you the reason for choosing the PL side DDR of zynq, which is enough for nanny-level teaching. . .

4. Overall design idea and scheme

The overall design idea and scheme are as follows:

Video input path

The motherboard of the desktop computer has a PCIE slot, and the FPGA board is connected to the computer motherboard through the PCIE slot. The QT host computer program calls the Xilinx XDMA official API to capture the computer desktop image in real time as a video input, and sends the collected image to the FPGA board through the PCIE bus. card, as the input source of the FPGA board;

PCIE data cache path

After receiving the image data from PCIE, XDMA caches the image to the PL side DDR3 of zynq;

Video output path

VDMA_1 is configured in read-only mode, reads out the cached video, calls AXIS to video out to convert the AXIS video stream from VTC to VGA timing video stream, and has an ADV7511 encoding chip on board to encode the RGB data of the VGA video stream It is a TMDS differential video output display; ADV7511 is configured by zynq's i2c;

5. Detailed explanation of vivado project

Development board FPGA model: Xilinx–zynq–xc7z100ffg900-2;
development environment: Vivado2019.1;
input: PCIE X8;
output: HDMI; ADV7511 encoding; application : QT host
computer display test; As follows: The estimated FPGA resource consumption and power consumption after the comprehensive compilation is completed are as follows:

6. Detailed explanation of SDK project

The SDK mainly completes the i2c configuration of the HDMI codec chip, the register configuration of the VDMA, the configuration of the VTC, etc. The SDK part is implemented in C language, and the code structure is as follows:

7. Driver installation

Provide Win system driver, the directory is as follows:

Provide Win and Linux driver,
please refer to my previous article for the specific installation tutorial of the driver: Click to go directly

8. QT host computer software

QT speed measuring host computer: provide source code and executable program, the released version is QT5.6.2; the location is as follows:

9. Board debugging and verification

Open the host computer test program for PCIe display test, open the display software pcie2screen in the figure below, the software is in the following location, the experimental results are as follows: after opening the

host computer, click start screen mapping, the current computer screen will be captured, and then transferred to DDR3 through PCIe Among them, through continuous capture, a continuous video can be formed:

the desktop image of the host computer captured by HDMI output PCIE;

10. Welfare: acquisition of engineering code

Benefits: Obtaining the engineering code
The code is too large to be sent by email, and it is sent by a certain degree network disk link. The
method of data acquisition: private, or the V business card at the end of the article.
The network disk information is as follows: