Table of contents
1 Introduction
Currently, there are two schemes for FPGA to implement CameraLink video codec:
one is to use a dedicated codec chip, such as a typical DS90CR287; the other is to use FPGA to implement codec, and use FPGA serdes resources to achieve deserialization. FPGA resources and serdes resources are unnecessary. The disadvantage is that the operation is more difficult and requires a higher level of FPGA.
This article describes in detail the implementation design scheme for the FPGA to capture the Base mode decoding output of the CameraLink camera. The idea is that the CameraLink camera is input to the FPGA board, and the FPGA uses internal logic resources to implement LVDS video decoding, and parse out the pixel clock, line synchronization signal, and field synchronization. Signal, data effective signal, and pixel data, and then convert the video to Xilinx's AXI4-Sream video stream, send it to the DDR3 cache through VDMA, then read out the video and then output the video through the HDMI interface through AXI4-Sream to Video Out
, This is a commonly used routine for Xilinx image processing, and it can be described as a very delicate solution, huh, huh. . .
After the engineering code is compiled and passed, it can be debugged and verified on the board, and the project can be directly transplanted. It is suitable for students in school to do graduation design, graduate project development, and also for in-service engineers to do project development. It can be applied to digital imaging and images in medical, military and other industries. Transmission field;
provide complete and smooth project source code and technical support;
the method of obtaining project source code and technical support is at the end of the article, please be patient to read the end;
2. Basics of CameraLink protocol
Regarding this part, many bloggers on the Internet have explained it. I found a few articles to recommend brothers to learn theoretical knowledge: the
first link: click to go directly to
the second link, which is what I wrote before: click to go directly
3. Currently I have the CameraLink transceiver project
My CameraLink video column has many CaeraLink video codec solutions for FPGA, including CaeraLink receiving, CaeraLink sending, CaeraLink ordinary output display, and CaeraLink video splicing output, etc. The column link is as follows: Welcome to view: Click to go directly
4. Design plan
The detailed design scheme is as follows:
Input CameraLink camera
The CameraLink camera model is RS-A5241-CC107-S00 color CameraLink camera of Beijing Microvision. The camera can be configured as Base mode or Full mode through the serial port. This project uses Base mode; the resolution is full-frame 2560 2048 , The frame rate can reach 107fps; the project configuration is 1280 1024;
LVDS video decoding
The design block diagram of the LVDS video decoding module is as follows:
When the CameraLink decoding module is in Base mode, the input signals are as follows:
1 channel of differential clock, 4 channels of differential data; use Xilinx official IDELAY and ISERDES source languages to realize serial-to-parallel conversion;
IDELAY source language is used to delay so that the CameraLink video data is stable during FPGA sampling;
the function of the ISERDES source language is to realize the serial-to-parallel conversion of CameraLink video data;
the entire CameraLink decoding module is implemented strictly according to the design block diagram, mainly calling the source language, so there is nothing Speaking of it, look at the code specifically, the amount of code is very small;
the parameter configuration of the CameraLink decoding module is as follows:
these two parameters can be freely configured to adapt to different modes of the CameraLink camera; the specific configuration is as follows:
video cache
The decoded video is converted to Xilinx's AXI4-Sream video stream, which is sent to the DDR3 buffer via VDMA, and then the video is read out and then output through the HDMI interface through AXI4-Sream to Video Out, which is a common routine for Xilinx image processing; The entire video cache architecture is centered on VDMA, and all of them call Xilixn's IP implementation. You only need to configure the IP to use it. The configuration here includes both the UI interface configuration and the software configuration. Since this project uses the Kintex 7-bit platform, it is called The MicroBlaze soft core runs the SDK to configure these IPs;
video output
The IP of Video Mixer is called here, because the CameraLink camera configuration is 1280 1024, and the output resolution is 1920 1080, so use Video Mixer to make a black background of 1920 1080, and then superimpose the camera video of 1280 1024 on it
; call AXI4-Sream to Video Out outputs VGA timing, and a sil9022 chip on board completes the VGA to TMDS conversion and finally displays it on the HDMI interface output monitor;
software configuration
So call the MicroBlaze soft core to run the SDK to configure these IPs, configure the CameraLink camera, configure the sil9022 chip, and complete the human-computer interaction with the upper computer; call
an AXI-UART to complete the human-computer interaction with the upper computer, that is, the upper computer through the serial port The debugging assistant sends instructions to the program;
call an AXI-UART to complete the configuration of the CameraLink camera, the configuration of this project is 1280*1024 resolution, Base mode;
call an AXI-IIC to complete the configuration of the sil9022 chip;
5. Detailed explanation of vivado project
Development board FPGA model: xc7k325tffg676-2;
development environment: vivado2019.1;
input: CameraLink camera; Base mode; 1280 1024 resolution;
output: HDMI, 1920 1080 resolution;
The design of Bolck Design is as follows:
The integrated engineering code structure is as follows:
The estimated FPGA resource consumption and power consumption after comprehensive compilation is as follows:
The SDK software program structure is as follows:
6. Board debugging and verification
Since the CamerLink adapter board is inconvenient to leave the country, only the FPGA board and the corresponding CamerLink adapter board interface are shown, as follows: The
use and configuration process of the project is relatively complicated, and I feel that there are too many steps to write here, so I wrote a special article on how to use it. The documentation of the commissioning manual is placed in the data package, and the path is as follows:
Attention! ! !
Notice! ! !
Notice! ! !
After downloading this project, please put the file in a folder with the shortest path, because the path is too long may cause project compilation failure; also, this project has tried the HLS IP core, please update the official patch file before compiling , otherwise an error will be reported during synthesis. The file download and update methods for updating the official patch file are written in the above document, remember to read it carefully; the output effect is as follows
:
7. Welfare: acquisition of engineering code
Benefits: Obtaining the engineering code
The code is too large to be sent by email, and it is sent by a link to a certain network disk.
Data acquisition method 1: private, or the V business card at the end of the article.
The network disk information is as follows:
