Preamble: I have seen a lot of information on IC or FPGA design tool systems on eetop forums or other sites, but they are not very comprehensive. So here try to do a 2012 version of the EDA tool introduction.
FPGA design
Basic design tools, QUARTUS, ISE, Synplify pro, Modelsim.
Mainstream FPGA devices are mainly two, Altera and Xilinx. So the two QUARTUS and ISE are the basis of the FPGA design process.
Of course, synplify pro also supports each.
Modelsim has both OEM version and SE version. There are various kinds of models. As a seamless link in the ISE design process, Modelsim SE is a good choice.
IC Design Tools
Basic Design Tools: Verdi, DC, PT, FM, SoC Encounter, and Calibre.
The world's three major EDA manufacturers generally refer to Cadence, Synopsys, Mentor Graphics, and the top four include Springsoft. As far as I understand it, Synopsys is mainly strong in the front end, and DC and PT are recognized standards. Cadence is in the back-end, whether it is RF, digital, or PCB level, its back-end wiring tools are widely used. MG's tools are a bit scattered. Calibre for physical verification and parameter extraction is also a sign off tool used by most companies, and Modelsim is also widely used. Recently, CatapultC's SystemC synthesis tool has also emerged to compete with Synopsys' Synphony C Compiler. . In my personal understanding, the popularity of MG tools is mainly due to its platform friendliness, almost all tools can be run on windows, which is difficult for the first two to do. Springsoft's most prominent tool may be Verdi (now Verdi3), which has been transitioned from Debussy, mainly for code error checking.
Code troubleshooting tools: Synopsys' LEDA (the easiest), Springsoft's nLint, Spygalss (the most comprehensive, can do CDC)
Simulation: Synopsys VCS, Cadence NC-Verilog, Verilog-XL, and MG's Modelsim and Questasim (there is not much difference in commands between the two, but the latter is mainly for major verification methodologies, and supports SystemVerilog more Okay)
Synthesis: DC for S, Buildgates for Cadence.
Timing: PT for S, pearl for Cadence
Layout tools: Virtuoso from Cadence, laker from Springsoft
P&R: ICC for S, Astro, SoC Encounter for Cadence (now EDI)
DRC, LVS, parameter extraction: S's Herclues, StarRC (Herclues for physical verification, StarRC for parameter extraction), Cadence Diva/Dracula/Assura (Assura needs to be installed separately) and MG's Calibre
Spice Tools: Hspice from S and Spectre from Cadecen
--update(0810):
The design part of Synopsys is the Galaxy Design System, and the verification part is the Discovery platform.
Full process design from front to back, VCS, DC, DFTC, Formality, Prtimetime, TetraMAX(ATPG)
The back end is Hercules(DRC, LVS), ICC(including Design Planning), parameter extraction Star-RCXT.
Sign off, STA is Primetime, SI is PT-SI, transistor simulation is Hsim (Nanosim, both belong to the FastSpice family, different from Hspice and Spectre, the specific difference is not clear), power is Primerail (from Astro-rail)
Many tools in the whole process of Cadence have not been touched ( ref_link )
Through the related products in the right column of the link, it can be found that the encounter family still has many products corresponding to Synopsys, but they are all the names of the encounterr. The often mentioned APR tool is actually the encounter design implementation (EDI) system. This is a more professional term.
mentor
The previous statement about mentor is not very accurate. Although it has a strong correlation with win, it is found that many of the products of mentor follow the verification route. Whether it is functional simulation, or PCB level or physical verification, it is the route to verification. The physical verification is of course Calibre, and mbistarchitect is also a product used in the industry to do mbist long.