EDA electronic design technology and application
Electronic design automation (English: Electronic design automation, abbreviation: EDA) refers to the use of computer-aided design (CAD) software to complete the functional design, synthesis, verification, physics of very large scale integrated circuit (VLSI) chips. Design (including placement, routing, layout, design rule checking, etc.) and other processes are designed.
Known as the "mother of chips", EDA is the cornerstone industry of electronic design. The EDA market with tens of billions of dollars has built the foundation of the entire electronics industry. It can be said that "whoever masters EDA will have the dominance in the chip field.
" Faced with the crisis of "stuck neck" of key core technologies in many fields, the The constraints in the field of chip technology are particularly serious. It is urgent to break the monopoly as soon as possible and let the key chip technology no longer be controlled by others.
The localization of EDA chip design software is equally important to the breakthrough in the chip field as the manufacturing of lithography machines.
Before the advent of electronic design automation, designers had to manually complete the design, wiring, etc. of integrated circuits because the so-called integrated circuits at that time were far less complex than they are today. The industry began to use geometric methods to make tapes for circuit photoplotters. By the mid-1970s, developers should try to automate the entire design process, not just automating mask sketches. The first circuit layout and routing tool was successfully developed. The Design Automation Conference was created during this period to promote the development of electronic design automation.
The next important stage in the development of electronic design automation was marked by the 1980 paper "Introduction to VLSI Systems" by Carver Mead and Lynn Conway. This seminal paper presents new ideas for chip design through programming languages. If this idea is realized, the complexity of chip design can be significantly increased. This is mainly due to the considerable improvement in the performance of the tools used for logic simulation and functional verification of integrated circuits. With the development of computer simulation technology, the design project can be simulated before the actual hardware circuit is constructed, the requirements for manual design of chip layout and wiring are reduced, and the software error rate is continuously reduced. To this day, although the languages and tools used are still evolving, the approach of designing and verifying the expected behavior of circuits through programming languages, and using tool software to synthesize low-level abstraction (or "back-end") physical designs is still It is the basis of digital integrated circuit design.
Since 1981, electronic design automation has gradually begun to be commercialized. In 1984, the Design Automation Conference also held the first sales exhibition on the theme of electronic design automation. Gateway Design Automation introduced Verilog, a hardware description language in 1986, which is now the most popular high-level abstraction design language. In 1987, with funding from the US Department of Defense, another hardware description language, VHDL, was created. Modern electronic design automation design tools can recognize and read different types of hardware descriptions. Various simulation systems produced according to these language specifications are quickly introduced, allowing designers to directly simulate the designed chips. Later, the development of technology focused more on logic synthesis.
The design of digital integrated circuits is relatively modular (see integrated circuit design, design closure (Design closure) and design flow (Design flow (EDA))). The manufacturing process of semiconductor devices requires a standardized design description, and the high-abstract description will be compiled into the form of information units (cells). The designer does not need to consider the specific hardware process of the information unit when designing the logic. Using a specific integrated circuit manufacturing process to implement a hardware circuit, an information unit implements a predefined logic or other electronic function. Most semiconductor hardware manufacturers provide "component libraries" for manufactured components and provide corresponding standardized simulation models. Compared with digital electronic design automation tools, most electronic design automation tools of analog systems are not modular, because the functions of analog circuits are more complex, and the interaction of different parts is strong, and the law of action is complex, and most electronic components do not. So ideal. Verilog AMS is a hardware description language for analog electronic design. In this article, designers can use the hardware verification language to complete the verification work of the project. The latest development trend is to integrate the description language and the verification language into one, a typical example is SystemVerilog.
With the expansion of integrated circuits and the development of semiconductor technology, the importance of electronic design automation has increased dramatically. Users of these tools include hardware technicians in semiconductor device manufacturing centers, whose job is to operate semiconductor device manufacturing equipment and manage entire job shops. Some design-focused companies also use electronic design automation software to assess whether their manufacturing departments can adapt to new design tasks. Electronic design automation tools are also used to import designed functions into semi-custom programmable logic devices like field programmable logic gate arrays, or to produce fully custom application-specific integrated circuits.
situation
Today's digital circuits are very modular (see Integrated Circuit Design, Design Convergence, Design Process (EDA)), and the front end of the production line standardizes the design process and divides the design process into many "cells", regardless of technology , and then the cells implement logic or other electronic functions with specific integrated circuit technology. Manufacturers typically provide libraries of components and simulation models that conform to standard simulation tools to the production process. An analog EDA tool is less modular because it requires more functionality and requires more interaction between parts, which are generally less desirable.
In the electronics industry, EDA plays an increasingly important role due to the increasing scale of the semiconductor industry. Manufacturers using this technology are mostly foundry manufacturers engaged in the manufacture of semiconductor devices, and design services companies that use EDA simulation software to evaluate production conditions. EDA tools are also used in the programming of field programmable logic gate arrays.
EDA covers all aspects of electronic system design
Electronic Design Automation (EDA) technology refers to a complete set of automated processes including circuit system design, system simulation, design synthesis, PCB layout design and plate making. With the rapid development of computer, integrated circuit and electronic design technology, EDA technology has gone through the development process of Computer Aided Design (CAD), Computer Aided Manufacturing (CAM), Computer Aided Testing (CAT) and Computer Aided Engineering Design (CAE). Become the pillar industry of the electronic information industry.
There are many EDA product lines. According to different application scenarios of EDA tools, EDA tools can be divided into five categories: digital design, analog design, wafer manufacturing, packaging, and system. Among them, the system can be subdivided into PCB. , Flat panel display design tools, system simulation and prototype verification and CPLD/FPGA design tools, etc.
Digital design tools are mainly tools for digital chip design, a collection of a series of process point tools, including function and index definition, architecture design, RTL editing, functional simulation, logic synthesis, and static timing simulation (Static Timing Analysis, STA) , formal verification and other tools.
Analog design tools are mainly designed for analog chips, including layout design and editing, circuit simulation, layout verification, library feature extraction, RF design solutions and other product lines.
Wafer manufacturing tools are mainly design tools for fabs/foundries. These tools are mainly used to assist fabs in developing processes, realizing functions such as device modeling and simulation, and generating PDK. PDK is an important tool for wafer fabrication. The role of the important bridge between the circular factory and the design manufacturer shows that the EDA tool and the process are closely bound, and with the advancement of Moore's Law, it needs to be continuously upgraded and iterated. Wafer fabrication tools include device modeling, process and device simulation (TCAD), PDK development and verification, computational lithography, reticle calibration, reticle synthesis, and yield analysis.
Packaging tools are mainly design, simulation, and verification tools for chip packaging, including packaging design, packaging simulation, and SI/PI (Signal Integrity/Power Integrity) analysis. With the development of advanced chip packaging technology and the advancement of Moore's Law, the packaging forms are moving towards high density, high integration and miniaturization. Therefore, the requirements and difficulties for packaging have been greatly improved. At present, high-performance products require advanced integrated circuit packaging, such as Multi-chip heterogeneous integrated packaging, silicon-based high-density advanced packaging (HDAP), FOWLP, 2.5/3DIC, SiP and CoWoS, etc.
In the field of system EDA, EDA tools can be divided into PCB design, flat panel display design, system simulation tool (Emulation), and electronic system design on programmable devices such as CPLD/FPGA. The scope of EDA engineering continues to expand to downstream electronic system applications. Without the support of EDA technology, it is impossible to complete advanced electronic system design opportunities. Conversely, the continuous progress of manufacturing technology will inevitably bring forward new ideas for EDA technology. requirements.
In the system EDA, the printed circuit board (PCB) is mainly used as the carrier of the electronic system. Engineers usually solder the integrated circuit components on the PCB to complete the construction, control, communication and other functions of the entire electronic system. At present, the mainstream PCB tools include Cadence's Allegro, Mentor Graphics' Xpedition and Zuken's CR, etc. Domestic PCB manufacturers include Lichuang EDA and so on.
Flat panel display design is mainly used in panel R&D, production and manufacturing. The domestic EDA company Huada Jiutian already has the tools for the whole process in the field of flat panel display, basically covering the major domestic panel manufacturer customers.
System simulation tools (Emulation), different from traditional simulation tools (Simulation), mainly focus on system-level simulation and are widely used in scenarios where software and hardware joint development is accelerated. Traditional simulations focus more on single function or partial circuit simulation. . Siemens has launched the PAVE360 pre-silicon autonomous validation environment, which is primarily intended to support and facilitate the development of innovative autonomous vehicle platforms. PAVE360 provides a comprehensive environment for the research and development of next-generation automotive chips across the automotive ecosystem and multi-vendor collaboration. The system can not only realize automotive hardware and software subsystems, vehicle models, sensor data fusion, traffic flow simulation, and even Simulate the ultimate driving of a self-driving car in a smart city. At present, the three major EDA giants are laying out system simulation tools. The mainstream products include Synopsys' Zebu, Cadence's Palladium and Simens EDA's Veloce.
The most significant advantages of Complex Programmable Logic Device (CPLD) and Field Programmable Gates Array (FPGA) lie in short development cycle, low investment risk, quick time to market and large room for hardware upgrade. These two types of chips are relatively special chip types and need to work in conjunction with EDA tools. Manufacturers developing CPLD/FPGA need to develop a set of mature EDA download and verification tools to realize chip programming. From the brief design flow of CPLD/FPGA, it can be seen that the process is significantly reduced compared to the traditional chip design flow. At present, the mainstream EDA integrated development tools of programmable devices mainly include MAX+Plus and Quartus of Altera Company, Foundation and ISE of Xinlinx Company, ispDesignExpert and ispLever of Lattice Company, Synplify of Synopsys and Precision of Cadence.
According to the division of the integrated circuit industry chain, integrated circuit EDA tools can be divided into manufacturing EDA tools, design EDA tools and packaging and testing EDA tools. Device modeling and simulation tools belong to manufacturing EDA tools. Fabs (including foundries, IDM manufacturing departments, etc.) use manufacturing EDA tools such as device modeling and simulation, and yield analysis to assist in the development of their process platforms. , the process platform development stage is mainly completed by the fab. After it completes the design of the semiconductor device and manufacturing process, the model of the semiconductor device is established and provided to the integrated circuit design company through PDK or the establishment of IP and standard cell libraries (including chip design companies, semiconductor IP companies, IDM design departments, etc.).
Design EDA tools provide design services for chip designers based on PDK or IP and standard cell libraries provided by fabs or foundries. Chip designers use design EDA tools to complete chip design. Packaging EDA tools mainly provide the functions of packaging solution design and simulation, and help chip design companies to complete the design service of a chip's full life cycle.
The core aspects of digital design EDA are logic synthesis and place and route
Digital chip design mostly adopts the top-down design method, which can be divided into five steps:
1) Behavior-level design of the system, to determine the function and performance index of the chip (including chip area, cost, etc.)
2) Structural design, according to the characteristics of the chip , divide it into multiple sub-modules with clear interfaces and relatively independent functions
3) Logic design, which is implemented by using a regular structure, or using a verified logic unit
4) Circuit-level design to obtain a reliable circuit diagram
5) Convert the circuit diagram to physical layout.
1. System function description: Determine the chip specifications and make an overall design plan, which is the highest-level abstract description, including system function, performance, physical size, design mode, manufacturing process, etc. The function design is mainly to determine the realization plan of system functions , usually the timing diagram of the system and the data flow diagram between the sub-modules are given. This part of the work is mainly the design requirements put forward by the customer to the chip design manufacturer (Fabless, a waferless design company).
2. Logic design: Structure the system functions, usually with RTL (register transfer level) code (hardware description statements such as VHDL, Verilog, System Verilog, etc.), schematic diagrams, logic diagrams, etc. to express the design results, and complete the code of the relevant design specifications Write and ensure that the code is synthesizable and readable, and at the same time, it is necessary to consider the reusability of related modules.
3. Logic synthesis: Convert the circuit expression statements in the logic design into circuit implementation, using the standard circuit units provided by the chip manufacturer plus timing constraints (Timing Constraints) and other conditions, complete the RTL circuit with as few components and connections as possible The descriptions are mapped to synthesis library cells, resulting in a gate-level netlist that meets the requirements in area and timing. The logic synthesis step is the core link in the front-end design of the chip, which is related to the PPA level of the entire chip.
4. Physical design/layout: After logic synthesis, there are basically only the design results of logic and timing constraints, while physical design/layout is to make the circuit design closer to the real situation, that is, adding physical constraints (Physical Constraints), making The circuit becomes a chip that can actually be produced by a chip maker. The synthesized netlist and timing constraint files are imported into the tool of this link for placement and routing, parasitic parameter extraction is performed using relevant extraction software, and then fed back to the physically implemented placement and routing software, timing calculation and re-optimization are performed again until the timing sequence is met. and power consumption requirements.
5. Post-simulation/physical verification: The result of layout and wiring is the circuit after multi-level optimization. In order to ensure that the circuit is consistent with the circuit function described in the original system function description, post-simulation/design verification is required, mainly including design Rule Check (DRC), Layout Verification Check (LVS), Electrical Rule Check (ERC), Parasitic Parameter Extraction, etc.
Verification works throughout the design process. From the perspective of chip design, with physical implementation as the boundary, chip design can be divided into front-end (logical design) and back-end (physical design). During the implementation process, the design will be continuously optimized. Optimization may change the logic description method and structure. Introduce the risk of errors, so verification runs through the entire design process, and at each link, it is repeatedly ensured that the logic optimization process does not change the function, the timing meets the target requirements, the physical rules are not violated, etc., so a large number of verification processes and work are generated, involving multiple parties. Work together.
The front-end design mainly considers the logic and function levels, and the main purpose of the back-end design is the optimization of physical parameter constraints. The front-end design is more about the realization of the logic/function level. The implementation method is to connect the basic logic units to realize the logic functions required by the system. Generally, the front-end design does not consider the constraints of physical parameters, such as wiring between circuits. Factors such as the delay caused by the length of , only consider the electrical and physical parameters of the unit device. The back-end design focuses on adding physical constraints, such as the placement of some specific circuit modules, and the physical parameters of the connections between circuits are also considered in software optimization, so the back-end designed circuit is closer to meet the requirements actual circuit required.
In the comparison of analog and digital chip design process, the degree of automation of analog chip design is lower than that of digital chip design. Borrowing the concept of digital chip design, analog chip design can also be divided into front-end and back-end. Front-end design includes circuit diagram design and generation, involving a large number of algorithms, calculations, and hypothesis verification. From the perspective of automation, the degree of automation of digital chips in front-end design is obvious. Higher than analog chips, mainly because analog chips require engineers to manually select circuit topology and select appropriate components. In terms of back-end design, the back-end design of digital circuits is basically fully automated. The performance of EDA tools directly affects the performance of chip products. The back-end design of analog chips has a low degree of automation, especially in terms of layout steps.
The technological evolution in the post-Moore era drives the extension and expansion of EDA technology applications. The evolution direction of integrated circuit technology in the post-Moore era mainly includes three categories: continuation of Moore's Law (More Moore), expansion of Moore's Law (More than Moore) and Beyond Moore's Law (Beyond Moore). The further miniaturization of the feature size of the production process, the diversified development of chip functions aiming at increasing the multiple functions of system integration, and the integration of device functions and the diversification of products through three-dimensional packaging (3D Package), system-in-package (SiP), etc. change. Facing the direction of continuing Moore's Law (More Moore), the integration scale of a single chip has shown an explosive growth, which puts forward higher requirements for the design efficiency of EDA tools.
Facing the direction of expanding Moore's Law (More than Moore), as logic, simulation, storage and other functions are superimposed on the same chip, EDA tools need to have stronger support for complex functional design. Facing the direction of surpassing Moore's Law, the application of new processes, new materials, and new devices requires the development of EDA tools to achieve methodological innovations in key links such as simulation and verification.
Reference link
https://mp.weixin.qq.com/s/CuMEAGxTgtZIzvuKa3AwNQ
https://baike.baidu.com/item/%E7%94%B5%E5%AD%90%E8%AE%BE%E8% AE%A1%E8%87%AA%E5%8A%A8%E5%8C%96/10508153?fr=aladdin