In the backstage, some students privately messaged the interview questions that they want to verify, so this is it~
Q1. The difference between ":=" and /" in weight constraints
The := operator indicates that the weight of each value in the value range is the same, such as [1:3]:=40, which means that the probability of 1, 2, and 3 is 40/120;
The :/ operator means that the weight should be equally distributed to each value in the value range, such as [1:3]:/60, which means that the probability of getting 1, 2, and 3 is 20/60.
Q2. Similarities and differences between fork…join/fork…join_any/fork…join_none
fork...join: The inner begin end block runs in parallel, and does not enter the next phase until all threads have finished running.
fork...join_any: The internal begin end blocks run in parallel, and any begin end block can enter the next stage after running.
fork...join_none: The internal begin end blocks run in parallel, and can go directly to the next stage without waiting.
Similarities and differences between Q3.mailbox, event, and semaphore
Mailbox: Mainly used for data communication between two threads, send and get data through put function, get function and peek function.
event: The event is mainly used for a synchronous operation between two threads, and the operation synchronization between the two threads is performed through event triggering and event waiting. Use @(event) or wait(event.trigger) to wait, -> to trigger.
semaphore: The semaphore is mainly used for an interaction of resource access, and a thread can access a resource through key acquisition and return. Use the put and get functions to get the return key. Multiple at a time.
Q4. The difference between @(event_handle) and wait(event_handle.triggered)
@(event_handle): Triggered by the edge, the event will wait until it is triggered, blocking type;
wait(event_handle.triggered): level trigger, if the event is currently triggered, it will not cause blocking, non-blocking, when the event is triggered multiple times, avoid using wait.
Q5.task and function similarities and differences
function: There must be at least one input variable and one return value, which can only be used for pure numbers or logical operations;
task: Commonly used time-consuming statements can be built in, which may be used in time-consuming signal sampling or driving scenarios.
If you want to call a function, you can use both function and task to call it; if you want to call a task, it is recommended to use task to call, because if the called task has a built-in time-consuming statement, the method type that calls it externally must for task.
Q6. Benefits of using clocking block
Interface: It is a set of interfaces for encapsulating and bundling signals. If each signal is connected like in verilog, we need to define the interface signal at each layer. If there are too many signals, it is easy to cause human error, and the later reusability is not high. Therefore, using the interface interface to connect can not only simplify the code, but also improve reusability. In addition, the interface provides some other functions for synchronization between the test platform and the DUT and to avoid competition.
Clocking block: Inside the interface, we can define the clocking block, which can keep the signal synchronized. There are detailed setting operations for the sampling and driving of the interface, so as to avoid the interface competition between TB and DUT, and reduce our errors caused by signal competition. The sampling is advanced and the driving is behind to ensure that the signal will not compete.
Q7. The role and difference between synchronous FIFO and asynchronous FIFO
FIFO is a Simple Dual Port RAM whose address is incremented sequentially in hardware. It is divided into synchronous FIFO and asynchronous FIFO according to whether the clock domains of reading data and writing data are the same. Among them, synchronous FIFO means that the reading clock and writing clock are synchronous clocks. , often used for data caching and data bit width conversion; asynchronous FIFO usually refers to the frequency difference between the read clock and the write clock, that is, the FIFO driven by two asynchronous clocks, because the read and write operations are independent, it is often used for multi-bit Data is processed across clock domains.
Q8. Three major characteristics of OOP in SystemVerilog
Classes have three main features: encapsulation, inheritance, and polymorphism.
Encapsulation: By encapsulating some data and methods of using these data in a collection, it becomes a class.
Inheritance: Allows to get a new class through an existing class, and it can share the properties and methods of the existing class. Existing classes are called base classes, and new classes are called derived or extended classes.
Polymorphism: After obtaining the extended class, sometimes we will use the base class handle to call the extended class object. How can the method called at this time accurately determine the method we want to call? By making a virtual declaration of the method in the class, when calling When the base class handle points to the extended class, the method will be identified according to the object, and the method of the extended class will be called instead of the method in the base class. The methods in the base class and the extended class have the same name, but can be called accurately, which is called polymorphism.
Q9. Detailed understanding of the ref type
The ref parameter type is a reference
When passing an array to a subroutine, try to use ref to get the best performance. If you do not want the subroutine to change the value of the array, you can use the const ref type
Variables can be modified in a task and the result of the modification is always visible to the function that calls it.
Q10. How to use external constraints and what are the ways
Usage example:
class Packet;
rand bit [7:0] length;
rand bit [7:0] payload[];
constraint c_valid {length > 0;payload.size() == length;}
constraint c_external;
endclass
constraint Packet::c_external {length == 1;} //外部约束
Randomization is an extremely important knowledge point in SV. By setting randomization and related constraints, we can automatically randomize the desired data.
Weight constraints dist: There are two operators: :=n :/n The first one means that each value has a weight of n, and the second means that each value has a weight of n/num.
Conditional constraints if else and -> (case): if else is the same as normal use; -> After the previous conditions are met, the following events can be triggered.
Range constraint inside: inside{[min:max]}; the range operator can also directly use the greater than or less than symbol, and cannot be used continuously, such as min<wxm<max, which is wrong
Q11. What are code coverage, functional coverage, and SVA coverage measured?
Code coverage: It is the embodiment of the completeness of the RTL design code, including line coverage, condition coverage, FSM coverage, jump coverage, branch coverage, as long as the simulation can be collected, you can see which part of the DUT The code has not been moved. If there is a part of the code that has not been moved, check whether the case is not written.
**Functional coverage: **Compared with the spec to find out whether the design behaves correctly, you need to compare the progress according to the verification plan. A measure of which design features have been tested by the test program, the first option is to use more seeds to run the existing test program; the second is to establish new constraints, only when it is really necessary to resort to Directed testing, the easiest way to improve functional coverage is to just increase the simulation time or try a new random seed. The purpose of verification is to ensure that the design behaves correctly in the real environment. The design specification specifies how the device should operate, while the verification plan outlines how the corresponding functions should be stimulated, verified, and measured
**Assertion Coverage: **Used to check the relationship between several signals, it is often used to find errors, mainly to check timing errors, and measure how often assertions are triggered.
Q12. Why choose verification work
Because I like it, because I love it, because the industry needs it;
Q13. The characteristics of immediate assertion and concurrent assertion
Immediate assertion has nothing to do with timing. For example, when we randomize incentives, we will use immediate assertion. If the randomization is wrong, we will trigger the assertion and report an error.
Concurrent assertions are mainly used to detect timing relationships, because in many modules or buses, simply using coverage or transaction checks cannot fully detect the relationship between multiple timing signals, but concurrent assertions can use concise language to Monitoring, among other things, can also perform coverage detection.
There are three main levels of concurrent assertion usage:
The first is a Boolean expression. A Boolean expression is the smallest unit of an assertion. An assertion can be composed of multiple logical events. These logical events can be simple Boolean expressions. In SVA, signals or events can use commonly used operators , such as: &&, ||, !, ^, &, etc.;
The second sequence sequence is written. A sequence is a higher-level unit of a Boolean expression. A sequence can contain several Boolean expressions. At the same time, some new operators can be used in the sequence, such as ##, repetition operator, sequence operator;
The third is the writing of the attribute property. Property is a higher-level unit than sequence, and it is also the most commonly used module to form assertions. The most important property is that the implication operator (|-> |=>) can be used in property ;
Q14. Advantages of object-oriented programming in SystemVerilog
1. Easy maintenance
The structure designed with object-oriented thinking has high readability. Due to the existence of inheritance, even if the requirements are changed, the maintenance is only in partial modules, so maintenance is very convenient and low-cost.
2. High quality
At the time of design, existing classes that have been tested in the field of previous projects can be reused to make the system meet business needs and have high quality.
3. High efficiency
During software development, abstract things in the real world according to design needs to generate classes. Using such a method to solve problems, which is close to daily life and natural way of thinking, is bound to improve the efficiency and quality of software development.
4. Easy to expand
Due to the characteristics of inheritance, encapsulation, and polymorphism, a system structure with high cohesion and low coupling is naturally designed, which makes the system more flexible, easier to expand, and lower in cost.
Q15. How to ensure the completeness of verification
First of all, it is impossible to be 100% complete, that is, to traverse all combinations of signals, which is neither economical nor realistic. Therefore, it can only be verified by multiple verification methods to reduce potential risks as much as possible. Generally, there are these verification processes: ip-level verification, subsystem-level verification, and soc-level verification. In addition to these, there are also upf verification, fpga prototype verification, etc. means. Every time the front-end completes a stage, it needs to review and verify function points, test cases, and waveforms under special circumstances with the design and system.
The backend of the chip will also do some checks, such as sta, formality, DFM, DRC checks, etc., and will also insert some DFT logic for tape-out testing. The tape-out is back for testing, some bugs can be circumvented by software, some cannot be circumvented, and can only be filmed again.
Due to space limitations, IC verification interview questions will not be listed one by one. If you need interview questions, and want to understand the issues that need to be paid attention to on the resume, or the things that need to be prepared before the interview, you can ask the engineer first (all interview questions can be collar)
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