Digital IC verification high-frequency interview questions and answers (2)

Recently, some students in the backstage privately sent interview questions that they still want to verify, so this is it~

Q16. The difference between ":=" and ":/" in weight constraints

The := operator indicates that the weight of each value in the value range is the same, such as [1:3]:=40, which means that the probability of 1, 2, and 3 is 40/120;

The :/ operator means that the weight should be equally distributed to each value in the value range, such as [1:3]:/60, which means that the probability of getting 1, 2, and 3 is 20/60.

Q17. The difference between rand and randc

rand: means random, for example, there are 56 numbers, and the random probability of each time is 1/56;
randc: means periodic random, such as 56 numbers, the probability of the first random is 1/56, and the second random The probability is 1/55, and so on.

The meaning and usage of Q18.break, continue and return

The break statement ends the entire loop.
continue Immediately end this cycle and continue to execute the next cycle.
The return statement terminates the execution of the function and returns the value of the function (if any).

Q19. After the return statement in the function is executed, will the remaining code statements in the function still be executed?

After return, the remaining statements in the function cannot be executed, which terminates the execution of the function and returns the value of the function.

Q20. The difference between a flip-flop and a latch

Trigger: Clock triggered, controlled by the clock, the current input is sampled and output is generated only when the clock is triggered.

Latch: Triggered by the level, asynchronously controlled. The latch is equivalent to a channel when the enable signal is valid, and the latch maintains the output state when the enable signal is invalid. The flip-flops are triggered by clock edges and are controlled synchronously.

The latch is sensitive to the input level and is greatly affected by the wiring delay, so it is difficult to ensure that the output does not have glitches; the flip-flop is not easy to generate glitches.

Q21. Why use two-level flip-flops for synchronization

Using secondary triggers for synchronization can greatly avoid the occurrence of metastability:

As for why "beating twice" can reduce metastability, I think the root cause is that the register is a bistable device, and there are only two stable states of 0 and 1. Most of the time, even if the Q terminal of the first-stage Flop appears metastable, it will stabilize within one clock cycle, so that what is collected by the second-stage Flop is a stable value. "Two beats" takes advantage of this and cuts off the propagation of the metastable state.

What are the violations of Q22.setup and hold?

The setup time refers to the minimum time that the signal at the data input terminal must remain stable before the active edge of the clock.
The hold time refers to the minimum time that the signal at the data input terminal must remain stable after the active edge of the clock.

The hold time timing check ensures that new data does not overwrite the initial data by arriving at the D terminal prematurely before the flip-flops can stably output the initial data.

To sum it up in one sentence: Compared with Capture Edge, the current data to be transmitted must come early (setup time) and leave late (hold time).

How to use and, intersect, or, throughout, $past in Q23.SVA

and: Two sequences can be combined in a logical AND manner. When both sequences match, the entire attribute is successful.

Example:
property p;
sequence_a and sequence_b;
endproperty
[ Note ] The check start points of sequence_a and sequence_b must be the same, but the end points of the two can be different. The success point of the entire property is the last successful sequence of the two sequences The matching point is the success point of the attribute.
or: Two sequences can be combined in a logical or manner. When one of the two sequences matches, the entire attribute succeeds.
Example:
property p;
sequence_a or sequence_b;
endproperty
[ Note ] The check start points of sequence_a and sequence_b must be the same, but the end points of the two can be different. The success point of the entire property depends on the sequence that matches the earliest success, as long as there are two If one of the sequences matches successfully, the entire attribute is considered a match.

The expressions on both sides of intersect are sequences, not properties. When using intersect, you need to ensure that the sequences on both sides must start at the same time, and when the two sequences finally match at the same time, the intersect of the two sequences is considered to match, that is, two sequences The matching length must be the same. The intersect operator is very similar to the and operator, but and does not require that the two sequences match at the same time when they finally match.

In SVA, some signals are sometimes required to maintain a state during a sequence inspection process. At this time, the throughout operator can be used. When the state of these signals changes unexpectedly, the sequence inspection is deemed to fail.

past is mainly used to check whether the value of the previous clock cycle of the current expression (if number_of_ticks is not specified, it points to the previous clock cycle by default) is true, and $past returns true if the bit is true. Its format is as follows:
past(expression[,number_of_ticks]);
where number_of_ticks can specify to check the sampling value of number_of_ticks cycles before the current moment.

The difference between "->" and "=>" in Q24.SVA

@ (posedge clk) a |-> b After asserting the rising edge of clk, event a "starts to happen", and at the same time, event b occurs
@ (posedge clk) a |=> b After asserting the rising edge of clk, event a begins to occur, the next One clock edge later, the b event starts to occur.

Q25. How to close constraints

According to different needs, to select which constraint blocks are enabled and which constraint blocks are prohibited, you can use the built-in constraint_mode() function to turn on or off multiple constraint blocks; the rand_mode() function to turn on or off random variables.

Q26. What is the difference between deep copy and shallow copy?

If the elements in the copied object have only values ​​and no references, there is no difference between shallow copy and deep copy. Both will copy the original object and generate a new object. Modifying the value in the new object will not affect the original object. , the new object is completely separated from the original object.

If the elements in the copied object contain references (like a list that stores another list, which stores references to another list), then shallow copy and deep copy are different. Although shallow copy copies the original object , but the reference is still saved, so modifying the value in the reference in the new object will still change the value of the list in the original object, and the new object is completely separated from the original object and not completely separated. The deep copy is different, it will create a new reference in the original object, that is, create a new list, and then put the reference of the new list, so that the new object can be completely separated from the original object.

Q27. What are the commonly used methods for queues?

Commonly used methods of queues: insert, delete, push_back and pop_front
Push inserts, pop removes
the front of the front, and the back of the back

Q28. The difference between local and protected

If the access type is not specified in the class, the default type of the member is public, and the members can be accessed by subclasses and outsiders.
If the access type is specified as protected, then only the class or subclass can access the members, and the outside cannot.
If the access type is specified as local, only the class can access members, and neither subclasses nor externals can access.

Q29. What are the common debugging methods?

1. Print display
2. Set breakpoint
3. Waveform analysis

Q30. Harm of metastable state

Metastability is the failure of a flip-flop to reach an identifiable state within a specified period of time.
The metastable state violates the timing sequence and cannot be stabilized within the specified time, and the metastable state has a transmission function, which will be passed to the flip-flop of the next stage, resulting in circuit errors. The metastable state eventually stabilizes, but it takes longer.

A total of 150 verification high-frequency interview questions sorted (including answers)

Due to space limitations, IC verification interview questions will not be listed one by one. If you need interview questions, and want to understand the issues that need to be paid attention to on the resume, or the things that need to be prepared before the interview, you can ask the engineer first (all interview questions can be collar)

Here is an entry: IC verification interview questions