Because of the reason of leaving soon, I need to sort out some things for handover. Let's summarize the experience of using Xilinx ZYNQ-7000, and hope it will be helpful to those who are new to it. It should be noted that before I came into contact with ZYNQ-7000, I did not do FPGA design, and the foundation of this part can be said to be zero. The focus of this year's work is not FPGA design, so the focus of this series of articles is on the use of tools and the design process of ZYNQ-7000, rather than how to design it. The hardware platform of this series of articles is: ZC702 (XC7Z020-1CLG484CES). The software used includes: PlanAhead, Xilinx Platform Studio, Xilinx Software Development Kit, all versions are 14.4. The serial port tool is Tera Term.
ZYNQ-7000 is an All Programmable SoC (All Programmable SoC) launched by Xilinx. The chip integrates ARM Cortex A9 dual-core and FPGA, so ZYNQ is a SoPC chip. Its structure is as follows:
The Processing System (generally referred to as PS) in the figure is the part of the processor (ARM Cortex A9 MPCore), which is very rich in resources. For details, please refer to the official Xilinx documentation. Programmable Logic (generally referred to as PL) is the programmable part (FPGA). The resources of this part vary with the level of the SoC chip. The lowest is Artix-7 (Zynq-7010 and Zynq-7020), and the highest is Kintex- 7 (Zynq-7030 and Zynq-7045). Of course, the FPGA in the SoC may use a higher Virtex series in the future, which is unknown.
The relationship between PS and PL:
The essence of PS is an ARM Cortex A9 MPcore, so if we don't use the programmable part, we can use only the PS part. That is to say, for the ZYNQ chip, the PS part can be used completely independently and does not depend on the PL part.
The essence of the PL part is Xilinx FPGA. In ZYNQ, we can regard PL as another "peripheral" of PS with reconfigurable characteristics, which can be used as a slave device of PS part and controlled by ARM processor. For example, when the number of serial ports of ARM (PS) is not enough, when the Ethernet interface is not enough, or when a video interface is required, the PL part can be used for expansion. Of course, we can also regard the PL part as a master device that is not controlled by the ARM processor and is equivalent to the ARM processor, and actively completes data interaction with external chips and interfaces. Even the PL part can also be used as the main device of the whole system, actively acquire and store data from the memory of the APU part, and can control the operation of the ARM processor. Therefore, in theory, the PL part can also operate independently like the PS part. But the limitation is that the PL section must be configured using the JTAG interface. If there is no JTAG interface, it cannot run independently, because both the PS part and the PL part of the ZYNQ must rely on the PS to complete the initial configuration of the chip.
随着嵌入式系统越来越复杂，功能越来越强大，往往在设计中既需要非常灵活的FPGA，又需要处理器去做一些控制，以及配合操作系统使用。传统的方法是使用一个FPGA芯片和一个处理器芯片，比如FPGA+ARM这种模式。不过在这种模式中，FPGA和ARM之间的通信往往会成为系统的瓶颈。但在ZYNQ7000中，将FPGA和ARM集成在一个芯片内部，两者之间的通信使用AXI_HP、AXI_GP、AXI_ACP三种接口通信，带宽可达吉比特，基本上不会存在二者通信带宽不足的问题。当然，传统上也有在FPGA上实现一个软核（比如Altera 的 Nios II，Xilinx的Picoblaze 、Micoblaze等），这样对于一些对处理器要求不高的场合是可以胜任的，但如果对于处理器要求比较高的场景，这种软核的性能往往是捉襟见肘。而且软核会占用一部分PFGA的资源。所以ZYNQ系列实现FPGA和硬核的集成，对于嵌入式开发设计可以说是具有里程碑意义的一件事。
Xilinx为ZYNQ的开发提供了三个主要软件：PlanAhead、Xilinx Platform Studio（XPS）、Xilinx Software Development Kit（SDK）。当然，关于这三个软件的定位以及作用，Xilinx以及网上都有很详细很官方的说明，我就不赘述了。我个人理解PlanAhead就是做整个硬件环境搭建，系统集成的。XPS可以从PlanAhead直接调用，主要用于处理器部分的开发设计。SDK是Xilinx对Eclipse的改装，主要用于软件部分的设计。当然，目前Xilinx已经推出了新一代的设计软件Vivado，详情可参加Xilinx官网。
当然，ZYNQ系列的芯片本身的设计与结构就很复杂，其涉及到的技术更是非常之多，因为本系列文章的定位，不会对这些进行总结。而且其实也没有必要，这些东西都可以在Xilinx官方提供的文档中找到。我只会总结一些文档中没有提到的，或者没有系统概括总结的东西。
PS: This series of articles does not cover anything related to my specific work, please do not ask.