Summary:
Xilinx FPGA Platform Ethernet Interface (Summary)
content
1. IP core configuration
After having the foundation of this series (1) and (2), we start to enter the practical operation. As a digression, FPGA is just a tool, you can use it, and more knowledge is outside the FPGA;
Xilinx provides us with an IP core called " Tri-Mode Ethernet MAC ", a three-mode Ethernet media access control layer, supporting full-duplex half-duplex gigabit, 100M, 10M and 2.5G Transmission rate, supports MII, GMII, RGMII, SGMII and TBI interfaces. The document is " PG051 " .
First enter ETH to find the triple-speed Ethernet IP:
Page 1: Transfer Rate
Set the maximum communication rate, 1Gb/s supports Ethernet speeds up to 1Gb/s. Four types of physical interfaces are supported, namely GMII, MII, RGMII and internal interfaces are available. 2.5 Gb/s only works if the physical interface is "internal", all other types are disabled.
Page 2: Interface Configuration
Physical interface:
Internal/MII/GMII/RGMII is optional, configure the type of the interface with the MAC, the interface type, you can review the MAC layer interface description in the series (2):
- MII support 10 Mb / s sum 100 Mb / s ；
- GMII supports 10 Mb/s, 100 Mb/s and 1Gb/s;
- RGMII is double edge sampling, supports 10Mb/s, 100Mb/s and 1Gb/s.
- Internal is when the kernel is generated, there is no physical interface available to connect to the internal PHY, such as Ethernet 1G/2.5G PCS/PMA or SGMII LogiCORE.
We choose RGMII here, and the use depends on the specific situation.
PS: RGMII can also use primitives to complete the design (IDDR, ODDR, IDELAYE2, ODELAYE2, IDELAYCTRL)
MAC Speed：
Tri-speed Ethernet IP can support 2.5Gb/s and 1Gb/s speed operation, 10Mb/s and 100Mb/s speed operation and full three-speed operation (10Mb/s, 100Mb/s and 1000Mb/s). The choices available for speed support selection depend on the physical interface selected:
- Only internal mode is available when the MAC data rate is set to 2.5 Gb/s.
- If the MAC data rate is set to 1 Gb/s, and GMII, RGMII, or Internal is selected, you can choose between triple-speed operation and 1 Gb/s operation.
- If the MAC data rate is set to 1Gb/s and MII is selected, only 10Mb/s and 100Mb/s operations are available.
We choose the three-speed mode here, and the transmission rate can be changed through the interface.
Management Type :
Select the "AXI4-Lite" option to include an optional management interface for IP configuration. The AVB option is not available if the AXI4-Lite management interface is not selected. The default setting is to select the AXI4-Lite management interface.
Once the management interface is enabled, select the Management Data Input/Output Interface (MDIO) option to include the optional MDIO interface. If this option is not selected, the resulting kernel does not have the MDIO logic required to manage objects in the physical layer.
If MDIO is enabled, select the "Add IO buffer for MDIO interface port" option to insert an I/O buffer for the MDIO interface port. This will create the bidirectional I/O bus mdio, and insert output buffers for mdc. If this option is not selected, the kernel will be generated using the mdio_i, mdio_o and mdio_t ports.
AXI4-Lite Frequency :
Specifies the frequency of the AXI4-Lite interface.
Page 3: Shared Logic
Choose to put in example design.
Page 4: Features
MAC Options :
Select whether to enable half-duplex logic. The default is full duplex mode.
AVB options :
Audio Video Bridging, AVB is used to enhance the real-time audio and video performance of Ethernet while maintaining backward compatibility with legacy Ethernet. If this option is selected, a fee-based Ethernet AVB endpoint license is required to enable kernel generation in addition to the tri-mode Ethernet MAC license.
Frame filter options :
A kernel can be generated with a frame filter that prevents frames that do not match this MAC from being received. .
Flow control :
Enable priority-based flow control support. Generally not. If checked, includes circuitry that generates PFC frames when transmitting and interprets PFC frames when receiving.
Statistics width :
Generate kernels with built-in statistics counters. Statistics counters can be 32-bit or 64-bit wide.
Statistics reset:
When statistical counters are included, logic may be included to ensure that the counters are cleared to zero on hardware reset. Selected by default.
2. Interface introduction
Focus on a few parts of the color mark:
Light green: Indicates the receiving part
What color is this: Indicates the sending part
Blue: Indicates the interface with the PHY
Yellow: indicates the configuration interface
The colors also represent the same clock domain.
PS: In the next example design, you will find that the example design encapsulates a layer of FIFO interface on the periphery, tx/rx_axis_fifo_*
| gtx_clk |
IN |
1 |
The global clock of the core, 125M for 1Gbps, 312.5M for 2.5Gbps |
| gtx_clk_out |
OUT |
1 |
This clock has a 0° phase shift relative to the gtx_clk input and is used for RGMII data transfer. |
| gtx_clk90_out |
OUT |
1 |
This clock has a 90° phase shift relative to the gtx_clk input for RGMII transmitter clock forwarding. |
| refclk |
IN |
1 |
For GMII or RGMI only, required for idle control, 200M to 300M, For UltraScale need to 300 to 1333M |
| rx_mac_aclk |
Out |
1 |
The clock used to receive data on the physical interface, the clock should be used to provide the clock for the physical interface receiving circuit and the RX AXI4-Stream receiving circuit. 312.5MHz corresponds to 2.5 Gb/s 125MHz corresponds to 1 Gb/s 25MHz corresponds to 100 Mb/s 2.5MHz corresponds to 10Mb/s |
| rx_reset |
Out |
1 |
Soft reset of active high RX section |
| rx_axis_mac_tdata |
Out |
8 |
Received user data |
| rx_axis_mac_tvalid |
Out |
1 |
Data valid signal for rx_axis_mac_tdata |
| rx_axis_mac_tlast |
Out |
1 |
Control signal for the rx_axis_mac_tdata port. Represents the last byte in the frame. |
| rx_axis_mac_tuser |
Out |
1 |
Control signal for rx_axis_mac_tdata. Set at the end of frame reception, indicating that the frame has errors. |
| rx_axis_filter_tuser |
Out |
X+1 |
Filter tuner output per frame. Can be used to only send data passed by a specific frame filter. For more information, see Frame Filters |
| tx_enable |
Out |
1 |
For RGMII, If it is 1Gbps, it is always high; If it is 100Mbps, one cycle in ten cycles is high If it is 10Mbps, one cycle in one hundred cycles is high |
| tx_ifg_delay |
IN |
8 |
Control Signals for Configurable Interframe Gap |
| tx_statistics_vector |
Out |
32 |
Status collection statistics |
| tx_statistics_valid |
Out |
1 |
Valid signal for tx_statistics_vector data |
| tx_mac_aclk |
Out |
1 |
The clock used to transmit data on the physical interface, the clock should be used to provide the clock for the physical interface transmit circuit and the TX AXI4-Stream transmit circuit. 312.5MHz corresponds to 2.5 Gb/s 125MHz corresponds to 1 Gb/s 25MHz corresponds to 100 Mb/s 2.5MHz corresponds to 10Mb/s |
| tx_reset |
Out |
1 |
Active high, the reset signal of the transmitter module |
| tx_axis_mac_tdata |
IN |
8 |
frame data to be transmitted |
| tx_axis_mac_tvalid |
IN |
1 |
Data valid signal of tx_axis_mac_tdata, active high |
| tx_axis_mac_tlast |
IN |
1 |
The last valid data of tx_axis_mac_tdata is high |
| tx_axis_mac_tuser |
IN |
1 |
Control signal for the tx_axis_mac_tdata port. Indicates an error condition in a frame that allows the MAC to send an error to the PHY, such as a FIFO underrun. |
| tx_axis_mac_tready |
OUT |
1 |
handshake signal. Set when the current data on tx_axis_mac_tdata has been accepted and tx_axis_mac_tvalid is High. At 10/100 Mb/s, this is used to meter data to cores at the correct rate. |
| pause_req |
IN |
1 |
PAUSE REQUEST: Upon request, the MAC sends a PAUSE frame when the current packet is complete |
| pause_val |
IN |
16 |
Pause Value: Inserted into the parameter field of the transmitted pause frame. |
| speedis100 |
OUT |
1 |
This output is valid when the kernel is running at 100Mb/s. It comes from bits[13:12] of the MAC speed configuration register. If no optional management interface is present, this is derived from configuration vector bits[13:12]. |
| speedis10100 |
OUT |
1 |
This output is valid when the core is running at 10 Mb/s or 100 Mb/s. It comes from bits[13:12] of the MAC speed configuration register. If the management interface does not exist, derived from the configuration vector bits[13:12] |
| rgmii_txd |
OUT |
4 |
Transfer data to PHY, interface data with PHY |
| rgmii_tx_ctl |
OUT |
1 |
Control signals to the PHY |
| rgmii_txc |
OUT |
1 |
Clock signal to PHY |
| rgmii_rxd |
IN |
4 |
Receive data from PHY |
| rgmii_rx_ctl |
IN |
1 |
Control signal from PHY |
| rgmii_rxc |
IN |
1 |
Clock from PHY |
| inband_link_status |
OUT |
1 |
Link status from PHY |
| inband_clock_speed |
OUT |
2 |
Link speed from PHY, this is configured by PHY hardware |
| average |
INOUT |
1 |
Data signal used to communicate with PHY configuration and status. Binds high if not used. Output data signal for communicating with PHY configuration and status |
| mdc |
OUT |
1 |
MDIO management clock: when using the optional management interface, derived from s_axi_aclk based on the provided configuration data. |
3. Supplementary Instructions
Further explanation of the above interface.
In the next article, we will continue the introduction of Example Design , focusing on the simulation content.