About Xilinx Zynq UltraScale+ MPSoC Power Management System
Kenshin FPGA development circle 
Zynq UltraScale+ MPSoC is the first true All Programmable heterogeneous processing SoC launched by Xilinx. It adopts a new generation of 16nm FinFET process technology and includes a scalable 32-bit or 64-bit multi-processor CPU for implementation. Dedicated hardware engine for graphics and video processing, advanced high-speed peripherals, and rich programmable logic resources. Unlike ASSP-based dedicated SoC solutions, Zynq UltraScale+ MPSoC can be provided by a flexible 32- or 64-bit data width processing system The greatest scalability, it can be applied to automotive driver assistance and safety systems (ADAS), wired and wireless high-speed communication systems, industrial Internet of Things and other fields. 
Figure 1 Xilinx Zynq UltraScale+ MPSoC internal design block diagram
Today, I would like to introduce to you the power management system of Zynq UltraScale+ MPSoC. Its internal power design uses multiple isolated "power zones", which are powered by characteristic external pins to achieve efficient power management. It is divided into four "power supply areas", which are the PS part of the battery power consumption area, the full power consumption area, the low power consumption area and the PL power consumption area. If these power areas are not customized in the design, power sharing can be achieved between them. 
Figure 2 Zynq UltraScale+ MPSoC internal power supply area division
The battery power consumption area is integrated with a backup power memory memory. Data can be stored in this memory device after power failure. It is mainly used to store encryption keys. At the same time, an external crystal oscillator provides a real-time clock to ensure normal operation after power failure. This part is powered by an external battery. The power consumption range is 180nW~3μW.
The low-power area includes the real-time processor unit, two ARM Cortex-R5 processors, static on-chip memory, platform management unit (PMU), configuration and security unit, and low-speed peripherals. The power consumption in this area ranges from 20mW to 400mW.
The full power consumption area includes application processor units, namely four ARM Cortex-A53 processors, GPU, DDR memory controller, and high-performance peripherals such as PCIe, USB3.0, display ports, and SATA interfaces. The power consumption of this area mainly depends on The number of active processor cores and the amount of calculations performed can consume up to several watts.
The PL power area includes programmable logic units, DSP modules, XADC, I/O ports, and high-speed serial interfaces. In addition, some models also include video codecs, PCIe Gen4 controllers, 100G Ethernet MAC units, etc. . The power consumption of this area is mainly related to the amount of programmable logic resources occupied and the clock frequency.
In addition, each power consumption area can be further divided into different "power islands" to achieve more detailed power supply scheme configuration for each unit. This power management architecture provides API interfaces for the application processor unit and real-time processor unit. It is designed with industry standards. Engineers can choose different power modes according to their needs. This enables or disables certain Zynq UltraScale+ MPSoC internal components to meet System function requirements are optimized for power consumption and heat dissipation.