A solid grasp of DCM, PLL, PMCD, and MMCM is the foundation of a robust clock design strategy.
Xilinx provides a wealth of clocking resources in its FPGAs that most designers use to some extent in their FPGA designs. However, for newcomers to FPGA design, when to use which of the four types of DCM, PLL, PMCD and MMCM, they are quite confused. None of Xilinx's existing FPGAs contain all four of these resources (see Table 1).
Each of these four categories is aimed at a specific application. For example, digital clock managers (DCMs) are suitable for implementing delay-locked loops (DLLs), digital frequency synthesizers, digital phase shifters, or digital spectrum spreaders. DCMs are also ideal for mirroring, transmitting, or rebuffering clock signals. Another clock resource, the Phase Matched Clock Divider (PMCD), can be used to implement a phase matched distributed clock or a phase matched delayed clock.
Phase-locked loops (PLLs) and mixed-mode clock managers (MMCMs) handle many of the same tasks, such as frequency synthesis, internal and external clock jitter filtering, and clock deskew. These two resources can also be used to mirror, transmit, or rebuffer the clock signal.
When mulling over design implementation details, keeping these common usages in mind will help clarify your clock choices. For long-term product development planning, compatibility across device families should be considered when developing an appropriate clocking strategy. Let's take a closer look at these clocking resources.
You can use DCM to multiply the input clock signal of a clock source to generate a high frequency clock signal. Similarly, the input clock signal from the high frequency clock source can be divided to generate the low frequency clock signal.
Digital Clock Manager
As the name implies, a digital clock manager (DCM) is a module that manages the clock architecture and facilitates the shaping and manipulation of clock signals. The DCM contains a delay-locked loop (DLL) that removes the skew of the DCM's output clock signal based on the input clock signal, thereby avoiding clock distribution delays.
The DLL contains a delay element and control logic chain. The output of the delay element is the delay of the input clock. The delay time depends on the position of the delay element in the delay chain. This delay manifests as a phase change or phase shift relative to the original clock, which is known as a "digital phase shift". Figure 1 shows a typical DCM block in a Virtex-4 device. According to the Virtex-4 FPGA User Guide (UG070, version 2.6), there are three different DCM primitives in Virtex-4.
In general, a DLL is similar to a PLL. Unlike the PLL, however, the DLL does not contain a Voltage Controlled Oscillator (VCO). A PLL will always store phase and frequency information, while a DLL will only store phase information. Therefore, the DLL is slightly more stable than the PLL. Both types, DLL and PLL, can be designed using analog and digital techniques, or a mix of both. But the DCMs in Xilinx devices are all digital.
Because DCMs can introduce delays on the clock path, you can use DCMs, for example, to precisely generate the timing of row and column access strobes for DRAM. Similarly, individual data bits on the data bus can arrive at different times. In order to sample data bits correctly, the clock signal at the receiving end must be properly synchronized with the arrival of all data bits. If the receiver uses the transmit clock, a delay in the clock signal from the transmitter to the receiver may be required.
Sometimes a design may require a higher clock frequency to run the logic on the FPGA. However, only clock sources with low frequency output can be used. At this point, the DCM can be used to multiply the input clock signal of the clock source to generate a high frequency clock signal. Similarly, the input clock signal from the high frequency clock source can be divided to generate the low frequency clock signal. This technique is called "digital frequency synthesis".
Designers use spread spectrum clocking and modulate the clock signal to reduce the peak electromagnetic emissions of the clock signal. The peaks of the unmodulated clock signal generate high electromagnetic radiation. But after modulation, the electromagnetic radiation is spread over a range of clock frequencies, reducing radiation at all frequencies. Generally speaking, spread-spectrum clocking is required when certain maximum electromagnetic radiation requirements are required and when high-speed processing is performed on an FPGA, such as a deserializer used by a receiver in a communication system. Therefore, the DCM in the FPGA will multiply the input spread spectrum clock signal to generate the high frequency clock signal internally. The output of the DCM must accurately follow the spread spectrum clock to maintain phase and frequency alignment and update deskew and phase shift. Deterioration in DCM phase and frequency alignment reduces receiver skew margin.
Mirroring a clock requires sending a clock signal out of the FPGA device and receiving it back. This method can be used to deskew board-level clock signals for a variety of devices. The DCM can send the clock signal from the FPGA to another device. This is because the input clock signal of the FPGA cannot be routed directly to the output pins, and no such routing path is available. If only the clock signal needs to be sent, using the DCM to send the clock signal to the output pins ensures signal fidelity. Alternatively, the DCM output can be connected to the ODDR flip-flop before the clock signal is sent. Of course, you can also choose not to use DCM and only use ODDR to send the clock signal. Often a clock driver needs to drive the clock signal to multiple components of the design. This can increase the load on the clock driver, leading to clock skew and other problems. In this case, clock buffering is required to balance the load.
Clocks can be connected to a series of logic blocks on the FPGA. To ensure that the clock signal has proper rise and fall times on registers far from the clock source (thus keeping the input and output delay within the allowable range), a clock buffer needs to be inserted between the clock driver and the load. DCMs can be used as clock buffers between clock input pins and logic blocks.
Finally, the DCM can also be used to convert the input clock signal to a differential I/O standard signal. For example, a DCM can convert an incoming LVTTL clock signal to an LVDS clock signal and send it out.
Phase-matched clock dividers
Designers can use the phase-matched clock divider (PMCD) to generate a phase-matched divided input clock signal. This is similar to DCM frequency synthesis for a divided clock. PMCD can also generate phase-matched but delayed clock signals in the design. In the latter case, the PCMD is able to maintain edge alignment, phase relationship and skew between the input clock signal and other PMCD input clock signals. Unlike DCM, existing PMCDs in Xilinx devices generate clock signals that are only divided by 2, 4, and 8 when the divider value is configurable. This means that the frequency of the clock signal generated by the PMCD is 1/2, 1/4 and 1/8 of the input clock signal. In a Xilinx device such as the Virtex-4FPGA, the PMCD is next to and on the same column as the DCM. Each column has two PMCD-DCM pairs. So the output of the DCM can drive the input of the PMCD.
Since the DCM also handles deskewing, designers can use PMCDs without DCMs as long as deskewing the clock is not required. It is also possible to connect two PMCDs in a column through dedicated pins. Figure 2 shows the PMCD primitives in Virtex-4 devices. See the Virtex-4FPGA User Guide (UG070, Rev 2.6) for details.
Mixed-Mode Clock Manager
Another type of clock resource, the Mixed-Mode Clock Manager (MMCM), is used to generate different clock signals with a set phase and frequency relationship to a given input clock. Unlike DCM, however, MMCM uses a PLL to do this. The Clock Management Module (CMT) in Virtex-6 FPGAs has two MMCMs, while the CMT in Virtex-7 has one MMCM and one PLL. The MMCM in Virtex-6 devices has no spread spectrum capability, so the spread spectrum on the input clock signal will not be filtered and will be passed directly to the MMCM output clock. But the MMCM of Virtex-7 FPGA has spread spectrum function.
The MMCM in Virtex-6 FPGAs requires the insertion of a calibration circuit to ensure correct operation of the MMCM after a user reset or user power-down. Xilinx ISE Design Suite version 11.5 and later can automatically insert the necessary calibration circuits during the MAP stage of the design. If using an earlier version of Xilinx ISE, you will need to manually insert the calibration circuit using the design files provided by Xilinx Technical Support. As a final note, when porting this design for implementation with ISE version 11.5 or later, the calibration circuit must be manually removed, or the auto-insertion feature must be disabled by appropriately setting the synthesis properties on each MMCM. See Xilinx Answer Record AR#33849 for details.
This problem does not exist for MMCMs in 7 series devices, as these FPGAs are only supported by ISE version 13.1 and later and the new Vivado Design Suite. Dedicated inter-MMCM routing is provided in the Virtex-6 family to allow the user to use global clocking resources for the rest of the design.
Figure 3 shows the MMCM primitives in a Virtex-6 FPGA. Refer to the Virtex-6 FPGA Clocking Resources User Guide (UG362, version 2.1) for a detailed description of each port. Figure 4 shows the MMCM primitives in Xilinx 7 Series FPGAs, see the 7 Series FPGAs Clocking Resources User Guide (UG472, Rev 1.5) for details.
Phase- locked loop
designers use phase-locked loops (PLLs) primarily for frequency synthesis. Multiple clock signals can be generated from one input clock signal using a single PLL. Used in conjunction with DCM, it can also be used as a dither filter. PLLs are available in Spartan-6, Virtex-5, and 7 series FPGAs.
There are dedicated "DCM to PLL" and "PLL to DCM" traces in both Spartan-6 and Virtex-5 . The PLL output in Spartan-6 and Virtex-5 is non-spread spectrum. For both devices, a PLL can be used in place of the DCM if the design uses multiple different clocks. The PLL clock output has a wide configuration range, while the output of the DCM is predetermined and not configurable. The choice of PLL and DCM also depends on the design requirements. However, if a phase shift is required, DCM should be chosen explicitly.
At the same time, PLLs in 7 series devices do not perform as much functionality as MMCMs. So while the MMCM is built on a PLL architecture, there are also separate PLLs in 7 series devices. Figure 5 shows the PLL primitives in a Virtex-5 FPGA. See the Virtex-5 User's Guide (UG190, version 5.4) for details on each port.
Design Migration
It is important to understand the differences between the four main clocking resources and their availability in different device families. At the same time, similar resources (such as DCMs) may not be functionally identical in different series. For example, DCMs in Spartan-6 FPGAs support spread spectrum clocking, but DCMs in Virtex-5 and Virtex-5 devices do not.
In addition to ensuring functionality, choosing the correct clocking resource for a given design is also important when planning future designs to migrate to higher end families. As shown in Table 1, MMCMs in the Virtex-6 and 7 series are backward compatible with DCMs in previous series. But it needs to be judged to what extent backward compatibility is supported, because all of these clocking resources are versatile and provide many different functions related to the clock. Compatibility must be well understood when planning long-term product development.