Broken thoughts:
As the first study notes of Basic Verilog, I intend to use this naming method to name the blog, which should help retrieval.
After simply browsing the code of some projects, I found that there are many nested relationships in it, so I decided to start with the basic module first, also for the fluency of the entire blog content.
If readers have any questions, you can also discuss with me at any time! Let's learn together and make progress together!
Table of contents
4 TestBench and simulation results
1 module function
The function of dividing the frequency of the clock through the counter can be used to modify the range of the output data by modifying the parameter part.
2 module code
//------------------------------------------------------------------------------
// clk_divider.sv
// published as part of https://github.com/pConst/basic_verilog
// Konstantin Pavlov, [email protected]
//------------------------------------------------------------------------------
// INFO ------------------------------------------------------------------------
// Divides main clock to get derivative slower synchronous clocks
//
/* --- INSTANTIATION TEMPLATE BEGIN ---
clk_divider #(
.WIDTH( 32 )
) CD1 (
.clk( clk ),
.nrst( 1'b1 ),
.ena( 1'b1 ),
.out( )
);
--- INSTANTIATION TEMPLATE END ---*/
module clk_divider #( parameter
WIDTH = 32
)(
input clk,
input nrst,
input ena,
output logic [(WIDTH-1):0] out = '0
);
always_ff @(posedge clk) begin
if ( ~nrst ) begin
out[(WIDTH-1):0] <= '0;
end else if (ena) begin
out[(WIDTH-1):0] <= out[(WIDTH-1):0] + 1'b1;
end
end
endmodule
3 Module Ideas
This module is relatively simple. When nrst=0, it resets; when it is not reset, it will use the counter principle to add one to out. The following will focus on two of the noteworthy places.
1.always_ff
Compared with the same always module in Verillog, this is an upgraded writing method in System (you can write a special machine for horizontal summary later).
In always_ff, ff is the abbreviation of flip_flop, which means that it is an edge-triggered trigger, and the keyword posedge or negedge needs to be added. In this example, it means that it is triggered by the rising edge of the clk signal.
2.logic
Reference blog: Detailed Explanation of SystemVerilog logic, wire, and reg data types - Migrant Worker Yuan Master's article - Know almost
The logic type is an upgraded part of System Verilog. The data type in Verilog is divided into two types: net type and variable. The net type uses assign for continuous assignment and can only be synthesized into combination logic; the variable type uses process assignment and may be synthesized . into sequential logic and may be synthesized into combinational logic .
The logic type, which can be continuously assigned or assigned by a procedure, is controlled by the compiler. But logic can only allow one input and cannot be driven multiple times. When wire is defined, the assignment is continuous assignment, while when logic is defined, the assignment is only the initial value, and the initial value cannot be synthesized.
4 TestBench and simulation results
`timescale 1ns / 1ps
module clk_divider_tb();
reg clk;
wire [31:0] out;
parameter half_cycle = 10;
initial
begin
// code that executes only once
// insert code here --> begin
clk = 0;
forever begin
#half_cycle clk = 1;
#half_cycle clk = 0;
end
// --> end
$display("Running testbench");
end
clk_divider #(
.WIDTH( 32 )
) CD1 (
.clk( clk ),
.nrst( 1'b1 ),
.ena( 1'b1 ),
.out( out )
);
endmodule
It can be seen from the simulation waveform that it is a simple counter principle, and then a combinational logic (such as an AND gate) can be connected to the out output to realize the frequency division operation.
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