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Since finishing STM32F4 Chinese Reference Manual (ST), STM32F4 Development Guide - Version Register (punctuality atom), cortex m3 and m4 Definitive Guide (English)
table of Contents
NVIC
This section associated with the kernel, does not appear in the reference manual, to be authoritative reference guide.
~. 8 ISER1
(the Set-the Enable Interrupt Registers) interrupt enable register group. CM4 interrupt kernel supports 256, with eight 32-bit registers to control, a control bit for each interrupt. Since STM32F4 maskable interrupt at most 82, only the ISER [0 ~ 2] effective, wherein ISER [0] of bit0 ~ 31 correspond Interrupt 0 ~ 31; ISER [1] The bit0 ~ 32 corresponding to the interrupt 32 to 63 ; ISER [2] the bit0 ~ 17 64 ~ 81 corresponding to the interrupt. ISER provided corresponding bit is 1, a particular interrupt is enabled.
Every corresponds to which specific interrupts, please refer to the line 188 stm32f4xx.h inside.
~. 8 ICER1
(the Clear-the Enable Interrupt Registers) Interrupt disabled register set. To clear an interrupt enable. Interrupt ISER same corresponding bits represent. By setting the bit to clear the interrupt.
~. 8 ISPR1
(the Set-the Pending Interrupt Registers) Pending Interrupt control register group. Interrupt ISER same corresponding bits represent. By setting can be an ongoing interrupt pending, interrupt the execution of the same level or higher.
~. 8 ICPR1
(the Clear-the Pending Interrupt Registers) solution linked to the interrupt control register group. Its role and ISPR contrast, disruption and ISER same as the corresponding bits represent. By setting 1, can be linked to pending interrupts solution.
~. 8 IABR1
(the Active Bit Interrupt Registers) activates interrupt flag register group, are read-only registers. Interrupt ISER same corresponding bits represent. If it is 1, it indicates that the bit corresponding to the interrupt is being executed. Cleared by hardware automatically after the interruption is finished.
240 ~ IPl
(the Priority Interrupt Registers) interrupt priority control register group. A 8bit register 240, each occupied 8bit maskable interrupt, so that a total of 240 may represent a maskable interrupt (which uses only STM32F4 82). IP [81] ~ IP [0 ] 81 - 0 Interrupt respectively. Each four maskable interrupt high (not lower nibble) sub-divided into priority and preemption priority. Preemption priority first, the child priority, according SCB-> AIRCR interrupt packet which is provided to determine the priority two half and a few bits.
GPIO
IO common configuration registers 8: MODER, OTYPER, OSPEEDR, PUPDR, ODR, IDR, AFRH and AFRL.
MODER
the GPIO port mode register (GPIO port mode register) for controlling the operating mode GPIOx port.
Each group has the IO IO ports 16, the register of 32 bits, each bit controls a two IO:
00-the IN; OUT-01; the AF-10;. 11-the AN;
OTYPER
the GPIO port output type register (GPIO port output type register) for output only mode.
The lower 16 bits of the effective register, each bit controls an IO port.
0-PP; 1-OD
OSPEEDR
the GPIO port output speed register (GPIO port output speed register), for output only mode, this register is used to control the output speed GPIOx, which controls an IO port register every 2 bits.
00-25MHZ; 01-50MHZ; 10-75MHZ; 11-100MHZ
PUPDR
the GPIO port pull-up / pull-down register (GPIO port pull-up / pull -down register) This register controls every two bits of a IO port, a drop-down setting.
00-NOPULL; 01-UP; 10-DOWN
The ODR
the GPIO port output data register (GPIO port output data register) is used to set a low output IO (ODRy = 0) or high (ODRy = 1).
An IDR
the GPIO port input data register (GPIO port input data register) for a read level of IO, if the corresponding bit is 0 (IDRy = 0), it indicates that the IO input is low, if it is 1 (IDRy = 1), it indicates that input is high.
EXIT
STM32F4 of EXTI external interrupt controller supports 23 / event requests.
EXTI_IMR
interrupt mask register (Interrupt mask register). The first 23 bits are valid. X interrupt request lines corresponding to the bit x. When the bit is set to 1 x, then turn interrupts the line.
EXTI_EMR
event mask register (Event mask register). Similarly IMR, except that the register is a shield for the event and open.
EXTI_RTSR
rising edge trigger selection register (Rising trigger selection register). The first 23 bits are valid. When the bit is set to 1 x, then turn on the rising edge of the line that triggered the interrupt / event.
EXTI_FTSR
falling edge trigger selection register (Falling trigger selection register). With RTSR, set the falling edge-triggered interrupts / events.
In the same interrupt line may be provided while rising and falling edge, i.e. either edge-triggered interrupts may.
EXTI_SWIER
software interrupt event register (Software interrupt event register).
SWIERx: software on the line x Interrupt (Software Interrupt on line x). When this bit is "0", write "1" is set in the corresponding pending bit EXTI_PR. If the interrupt is generated to allow EXTI_IMR and EXTI_EMR, the interrupt request is generated. This bit to "1" can clear it ( writing 1 to 0 ). SWIER bit is set, clears the corresponding bit is cleared in the PR .
EXTI_PR
pending register (Pending register).
PRx: pending bit (Pending bit). When the external interrupt line selected edge event occurs, the corresponding bit in this register will be set to 1. This bit to "1" it can be cleared ( by writing a 1 to 0 ), may be cleared by changing the polarity of the edge detection.
SYSCFG_EXTICR1~4
Located Chinese Reference Manual 8.2.4 ~ 8.2.7
SYSCFG external interrupt configuration register (SYSCFG external interrupt configuration register) is used to select the input source EXTIx external interrupt. Each EXTICR only lower 16 bits thereof, EXTICR [0] 0 ~ 3 ends just the GPIO
port, the respective other port EXTICR [1 ~ 3] management.
USART
USART_SR
status register (the Status Register).
RxNE (the Read Data Register Not empty, the read data register is not empty): This bit is set to 1 indicates that data has been received and can be read. May or Writing 0 clears this bit by reading USART_DR directly.
The TC (Transmission Complete, completion of transmission): When this bit is set to indicate the data has been transmitted in USART_DR completed. If you set the interrupt bit, it will generate an interrupt. This bit is cleared, there are two ways: 1) read USART_SR, write USART_DR. 2) Direct Writing 0.
Of ORE : Overflow error (Overrun error)
TXE : transmit data register empty (Transmit data register empty)
USART_DR
data register (Data register) This is a dual register containing the TDR and the RDR . When data is written to this register, the serial port will automatically sent, when data is received, is also present within the register.
When parity is enabled (USART_CR1 the PCE bit is set) is transmitted, the value written to the MSB (depending on the length of the data, or the MSB is bit 7 bit 8) will be substituted with the later check bit. When parity is enabled to receive, read the MSB is the received parity bit.
USART_BRR
baud rate register (Baud Rate Register)
DIV_Fraction : bits [3: 0] (valid when OVER8 = 0) is used to store the fractional part,
DIV_Mantissa : bits [15: 4] is used to store the integer portion, not the highest 16 use.
USART_CR1 ~ 3
control register (Control register) function provided for the lower 16 bits of the serial port.
OVER8 (Oversampling MODE) is the oversampling mode setting bit, OVER8 = 0 high precision, good fault tolerance, OVER8 = 1, when the difference between fault tolerance, speed. Generally set bit 0, i.e., 16-fold oversampling for better fault tolerance;
the UE for the serial enable bit, is set to enable the serial port;
M (Word length) word length selection bit when the bit is set to 0 when plus eight serial word length n stop bit, stop bit number (n) is a stop bit (sTOP bit) is provided to determine USART_CR2 default is 0;
the PCE (Control parity enable) parity enable bit is set to 1 to enable parity;
PS (parity selection) select the parity bit is set to 0, compared with even parity, or odd parity;
TXEIE (TXE interrupt enable) transmit buffer empty interrupt enable bit this bit is set to 1, when the TXE bit is 1 USART_SR in the serial interrupt is generated;
TCIE (transmission complete interrupt enable) transfer completion interrupt is enabled. This bit is set to 1 by software to send complete interrupt enable bit. Set this bit is 1, when 1 is from the TC bit USART_SR, the serial port interrupt is generated;
RXNEIE: RXNE Interrupt Enable (RXNE interrupt enable) RXNE receive interrupt enable buffer is not empty, set this bit is 1, when the ORE or USART_SR RxNE bit is 1, the serial port interrupt is generated;
the TE for the transmission enable bit , set to open the serial transmission function;
REs to receive an enable bit, set to open to accept the serial port functions.
TIM(2~5)
basic settings
TIMx_CR (~ 2. 1)
TIMx control register (TIMx Control Register).
The CEN : counter enable (Counter enable)
ARPE : auto-reload preload enable (Auto-reload preload enable)
bit is 1 TIMx_ARR buffer register ( at each update event (UEV), and only then the preload register contents (the ARR) is transferred to the shadow register.)
TIMx_DIER
TIMx the DMA / interrupt enable register (TIMx DMA / Interrupt enable register) 16 -bit registers.
The UIE : Update Interrupt Enable (Update interrupt enable)
TIMx_SR
TIMx status register (TIMx status register) is used to mark various events associated with the current timer / interrupt occurs.
UIF : Update interrupt flag (Update interrupt Flag)
● This bit is set by hardware when updating event occurs. But need to be cleared through software.
TIMx_PSC
TIMx prescaler (TIMx prescaler)
pre-divider value.
As TIMx_CNT
TIMx counter (TIMx counter).
The counter value.
TIMx_SMCR
TIMx from the mode control register (TIMx slave mode control register)
In TIMx_ARR
TIMx auto-reload register (TIMx auto-reload register) containing the shadow register.
Automatic reload value.
PWM related
TIMx_CCMR1~2
TIMx_CCMR1 control CH1 and 2, the control TIMx_CCMR2 CH3 and 4.
All bits in this register (CCXS) function in the input mode and output mode are different.
TIMx capture / compare mode register (TIMx Capture / Compare Register MODE)
OCxM : (the Output Compare X MODE) bit set mode, this section consists of three bits. A total of 7 modes can be configured. 1/2 PWM mode can be set to 110/111. The difference between these two PWM modes is the output level of opposite polarity.
CCxS : Capture / Compare Select x (Capture / Compare x selection), the direction (input / output) to set the default output channel. Note : TIM14 only one channel, only the lower eight valid.
TIMx_CCER
TIMx capture / compare enable register (TIMx Capture / Compare Register enable).
CCxE : Capture / Compare x Output Enable (Capture / Compare x output enable)
TIMx_CCR1~4
The total of four registers corresponding to four channels CH1 ~ 4.
TIMx capture / compare register x (TIMx capture / compare register x) in the output mode, the comparison value with the CNT value of the register, generates a corresponding action according to the comparison result.
Advanced Timer also need to configure: Brake and dead register (TIMx_BDTR)
