table of Contents
04、CCR(Capture/Comparex Register)
The shadow register was mentioned in the previous article " STM32 Basic Timer Detailed Explanation ", and the shadow register will be introduced in detail below.
01. Overview
In the timer block diagram, there is a small detail, and there is a shadow under some registers
Those with these shadows indicate that these registers have shadow registers.
There is also a description of the shadow register in the legend:
According to the control bit, after a U event occurs, the contents of the preloaded register are transferred to the effective register. This is the description of the shadow register.
The shaded register (AutoReloadRegister) means that physically this register corresponds to two registers. One is a register that the programmer can write or read, called preloadregister (preload register), and the other is invisible to the programmer , But the register that really plays a role in the operation is called shadowregister (shadow register).
There are 3 register names
AutoReloadRegister。
preloadregister。
shadowregister。
My understanding here is that AutoReloadRegister is a conceptual register. The definition of each bit can be found in the register table. It is composed of preloadregister and shadowregister. Our users have access to, and can modify or read the pre-loaded registers. ST just opens them up (the shadow registers are not open to users), which are actually the ARR registers.
The advantages of designing preloadregister and shadowregister are:
All the registers that really need to work (shadowregister) can be updated to the contents of the corresponding preloadregister at the same time (when an update event occurs), so that the operations of multiple channels can be accurately synchronized. If there is no shadowregister, or preloadregister and shadowregister are directly connected, that is, when the software updates the preloadregister, the shadowregister is updated at the same time, because the software cannot update multiple registers at the same time. As a result, the timing of multiple channels cannot be synchronized. Coupled with other factors (such as interrupts), the timing relationship of multiple channels may be unpredictable.
There are three types of shadow registers:
1、PSC(Prescaler)
2 、 ARR (AutoReloadRegister)
3、CCR(Capture/Comparex Register)
4、REPRegister
02、PSC(Prescaler)
In the description of the prescaler:
It is based on a 16-bit counter controlled through a 16-bit register(in the TIMx_PSC register).It can be changed on the fly as thiscontrol register is buffered. The new prescaler ratio is taken intoaccount at the next update event.
Excerpt from the STM32F207 Reference manual manual
Because the control register has a buffer function, the prescaler can be changed in real time. The new prescaler ratio will be adopted when the next update event occurs.
The timing diagram of the counter when the prescaler divides from 1 to 2
Here you can see that there is a shadow register in the prescaler register, but there is no control bit to control it. Its preload register and the shadow register are connected.
The working mode is as follows:
note:
In the ST manual, the shadow register is described as a buffer, and the shadow register of the prescaler is described as having a buffer function. among them
Here again it is described that the TIMx_ARR register is not buffered.
03 、 ARR (AutoReloadRegister)
Control bit:
It is explained in the time base unit as follows
The content of the preload register are transferred into theshadowregister permanently or at each update event (UEV), depending on theauto-reloadpreload enable bit (ARPE) in TIMx_CR1 register.
Excerpt from the STM32F207 Reference manual manual
The content of the preload register can be directly transferred to the shadow register, or it can be transferred to the shadow register every time an update event (UEV) occurs, depending on the automatic reload preload enable bit (ARPE) in the TIMx_CR1 register .
That is, the ARPE bit of TIMx_CR1 determines the time sequence of the preloaded register data transfer to the shadow register.
Counter timing diagram, update event when ARPE=0 (TIMx_ARR is not preloaded).
It can be seen from the above two figures that if the count up has not reached 0x36, the automatic reload register is modified to 0x36, and an action will occur when the count reaches 0x36.
Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded).
It can be seen from the above two figures that when counting upwards, before reaching 0x36, modify the auto-reload preload register to 0x36, and there will be no action when the count reaches 0x36, and the preload will be automatically reloaded at this time The register value is assigned to the automatic reload shadow register.
There are two ways to transfer from the preload register ARR to the shadow register, one is to update immediately, the other is to update after the trigger event; these two methods mainly depend on the "ARPE" bit in the register TIMx->CR1;
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ARPE=0, when the ARR value is modified, the value of the shadow register is updated at the same time;
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ARPE=1, when the ARR value is modified, the value of the shadow register can only be updated after the next event UEV occurs;
How to immediately change the value of the shadow register instead of the next event; the method is as follows
1. Set ARPE=0.
TIM_ARRPreloadConfig(ch1_Master_Tim, DISABLE );2. At ARPE=1.
TIM_ARRPreloadConfig(ch1_Master_Tim, ENABLE);After changing the preload register, we immediately set the UEV event, that is, change the UG bit of the EGR register, as follows
TIM1->ARR = period-1; //设置周期
TIM1->CCR1 = period>>1; //设置占空比50%
TIM_GenerateEventTIM1,TIM_EventSource_Update);//主动发生UEV事件,UG=1The working mode is as follows:
04、CCR(Capture/Comparex Register)
There is also a text description in the counter mode:
The UEV event can be disabled by software by setting the UDIS bit inthe TIMx_CR1 register. This is to avoid updating the shadow registerswhile writing new values in the preload registers。
Excerpt from the STM32F207 Reference manual manual
The UDIS bit in the TIMx_CR1 register is set to 1 by software to disable the update event UEV event. This avoids updating the shadow register when a new value is written to the preload register.
That is, the UDIS bit in the TIMx_CR1 register indirectly determines whether the preloaded register data is transferred to the shadow register.
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