Basic timer 6,7 register method configuration based on STM32F4XX

The basic timer has few functions, and it is easy to configure. Here is the official function explanation:

Key features of TIM6 and TIM7 The
features of the basic timers (TIM6 and TIM7) include:
● 16-bit auto-reload up-counter
● 16-bit programmable prescaler to divide the counter clock frequency (i.e. run-time modification ), with a division factor
between 1 and 65536
● Synchronization circuit for triggering the DAC
● Interrupt/DMA request generated on the following update events: Counter overflow
 

Personally, I think there are two functions: 1. Timing function 2. Synchronous circuit triggering DAC

Let's configure the timer function together

Configured by means of registers

Because the registers of the basic timer are less my train of thought is

First look at the picture:

 

        

Look at the picture again:

        

 Looking up from the bottom

ARR configuration automatic reset device register

PSC configuration prescaler

CNT doesn't need to look at this thing, the value automatically calculated after the timer is turned on

EGR has only one UG, write UG = 1 in the line of code before turning on the timer enable bit, it is written in the picture that CNT should start counting from zero 

SR status bit The basic timer is counting up and reaching the predetermined ARR will cause an overflow, this bit will be set to 1

The UDE bit in DIER is not related to DMA configuration, I don’t need it

              UIE bit update interrupt enable I need to configure interrupt enable this bit write 1

CR2 This configuration has nothing to do with this register TRGO.

CR1 CEN position one counter starts counting

        UDIS is used together with URS (debugging found the truth) UDIS is configured as 1 URS will not let the SR value no matter what is configured - we need to use interrupts, we need to configure URS to set it to zero

        URS looked at the manual and found that 0/1 can be used. I don’t want to use too many functions. If the URS is set to a counter overflow, the SR interrupt flag will be generated.

        OPM 0 update event counter is still counting, such as 0 to 255 to 255 update event, if configured interrupt, enter the interrupt service function. After entering, the counter CNT will not stop and will continue to count from 0 to 255 

Here I use 1 to stop counting when an update event occurs, which will not affect my concerns about interruption of subsequent use.

The worry is that if the interrupt service function takes 5us to run, but my timer 2us has an update event, it will crash.

        ARPE 0 does not perform buffering and 1 performs buffering. The understanding means that the value in CNT is always judged with the value of the shadow register (the value of the shadow register comes from ARR). If it is buffered, the value of the new ARR will not immediately enter the shadow register. It will still be the same as the shadow value written into the previous ARR. If it is not buffered, the value of the rewritten ARR will immediately enter the shadow register.

        Below is the code

/*
函数功能：初始化基本定时器6
函数参数：无
函数返回值：无
函数描述：无
*/
void DingShi6Init(unsigned short int PSC,unsigned short int ARR)
{
	NVIC_SetPriority(TIM6_DAC_IRQn,NVIC_EncodePriority(TIM6_DAC_IRQn,3,3)); //中断配置 抢占优先级3  响应优先级3级
	NVIC_EnableIRQ(TIM6_DAC_IRQn);	//使能中断
	RCC->APB1ENR |= (0X01 << 4);	//时钟源使能
	TIM6->PSC = PSC - 1;	//-1这个看手册 有解释的
	TIM6->ARR = ARR - 1;  //-1 也是需要看手册
	TIM6->DIER |= (0X01 << 0);	//中断使能
	TIM6->CR1 |= (0X01 << 3) | (0X01 << 2);	//不缓冲模式 OPM置一 URS置一 更新请求源选择  UDIS 0 更新开启
	TIM6->EGR |= (0x01 << 0); //开启前更新一下 CNT的值 让它运行前为0
	TIM6->CR1 |= (0X01 << 0);	//开启定时器计数
}


#include "usart.h"
void TIM6_DAC_IRQHandler(void)
{
	if((TIM6->SR & (0X01 << 0)))
	{
		TIM6->SR &= ~(0x01 << 0);
		printf("123\r\n");     //如果没有串口初始化的 可以用灯亮灭来反应
		TIM6->CR1 |= (0X01 << 0);
	}
}