Computer Organization principle and structure shown (Memory Design)

1, main memory organization and design (very important!)

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1) The semiconductor memory logic design

Refresh 2) dynamic memory

(1) Definition: replenished periodically charges the capacitor

(2) Reason: a dynamic memory rely capacitive charge storing information. Usually no power supply, the capacitive charge will bleed over time, the capacitor requiring regular supplemental charge to keep the information unchanged.

(3) Note refresh and rewrite the difference between:

• Refresh: nondestructive readout dynamic M, the need to add charge to maintain the original information.

• After the destructive readout rewritten to restore the original information.

(4) the maximum refresh interval: 2ms. In the meantime, it must be refreshed again for all dynamic unit.

(5) Refresh method:

• Read row.

• Refresh time line used - the refresh period (access period)

• The number of chips required for a refresh refresh cycle is determined by the number of rows in the chip matrix.

• Main memory access

  • CPU fetching: a CPU provides row and column addresses, random access.

  • Refresh Dynamic chip: providing a row address from the refresh address counter, the refresh timer.

Scheduler (6) refresh cycle:

1. Refresh focus: focus arrange all refresh cycles within 2ms.

2. Refresh dispersion: dispersing arranged in each refresh cycle access cycle.

3. Asynchronous Refresh: refresh cycle each dispersed arrangement within 2ms. Periodically refresh row.